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ics for communications acoustic echo canceller ace psb 2170 version 2.1 preliminary data sheet 10.99 ds 2
abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? - 2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. edition 10.99 published by infineon technologies ag, tr, balanstra?e 73, 81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. revision history: current version:preliminary data sheet 10.99 previous version: ds 1 page (in previous version) page (in new version) subjects (major changes since last revision) mips table added minor changes on some pages
psb 2170 table of contents page preliminary data sheet 3 10.99 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.4 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.6.1 full-duplex speakerphone for isdn terminal . . . . . . . . . . . . . . . . . . . .16 1.6.2 full-duplex speakerphone for pbx terminal . . . . . . . . . . . . . . . . . . . . .17 1.6.3 dect basestation with full-duplex speakerphone . . . . . . . . . . . . . . . .18 1.6.4 videophone with external line interface . . . . . . . . . . . . . . . . . . . . . . . . .19 1.6.5 videophone with software video compression . . . . . . . . . . . . . . . . . . . .20 1.6.6 full-duplex speakerphone in car environment . . . . . . . . . . . . . . . . . . .21 1.7 backward compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2 functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 full-duplex speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.1.1 echo cancellation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.1.2 noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.1.3 echo suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.1.4 comfort noise generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.1.5 noise controlled adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.2 line echo cancellation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3 dtmf detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.4 call progress tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.5 alert tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.5.1 universal tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.6 caller id decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.7 dtmf generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.8 analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2.9 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 2.10 universal attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.11 automatic gain control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.12 noise reduction unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 2.13 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 2.14 tone generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.15 peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.1 reset and power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.2 sps control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 3.3 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 3.4 abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
psb 2170 table of contents page preliminary data sheet 4 10.99 3.5 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 3.6 hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 3.6.1 frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 3.6.2 clock tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 3.6.3 afe clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 3.6.4 afe used for clock and frame sync gereration . . . . . . . . . . . . . . . . . .80 3.7 restrictions and mutual dependencies of modules . . . . . . . . . . . . . . . . . . .80 4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.2 ssdi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.2.1 ssdi interface - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.2.2 ssdi interface - receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.3 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 4.4 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 4.5 general purpose parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.5.1 static mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.5.2 multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.5.3 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 5 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 5.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 5.2 hardware configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 6.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 6.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
psb 2170 list of figures page preliminary data sheet 5 10.99 figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 3 psb 2170 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 4 full-duplex featurephone for isdn terminal . . . . . . . . . . . . . . . . . . . .16 figure 5 full-duplex featurephone for pbx terminal . . . . . . . . . . . . . . . . . . . . .17 figure 6 dect basestation with full-duplex speakerphone . . . . . . . . . . . . . . .18 figure 7 videophone with external line interface (hardware video codec). . . .19 figure 8 videophone with external line interface (software video codec) . . . .20 figure 9 full-duplex speakerphone in car environment. . . . . . . . . . . . . . . . . . .21 figure 10 functional units - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 11 functional units - speakerphone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 12 speakerphone - signal connections . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13 speakerphone - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 14 echo cancellation unit (fullband mode) - block diagram . . . . . . . . . . .28 figure 15 echo cancellation unit - double talk reduction . . . . . . . . . . . . . . . . . .29 figure 16 echo cancellation unit (subband mode) - block diagram . . . . . . . . . .31 figure 17 echo cancellation with noise reduction (subband mode) . . . . . . . . . .33 figure 18 coupling nr with wf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 19 echo suppression unit - states of operation . . . . . . . . . . . . . . . . . . . .35 figure 20 echo suppression unit - block diagram . . . . . . . . . . . . . . . . . . . . . . . .36 figure 21 speech detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 22 speech comparator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 23 speech comparator - acoustic echoes . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 24 speech comparator - interdependence of parameters . . . . . . . . . . . . .42 figure 25 echo suppression unit - automatic gain control . . . . . . . . . . . . . . . . .45 figure 26 comfort noise generator - integration into speakerphone . . . . . . . . . .48 figure 27 correlation adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 28 double talk detection adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 29 adaptive attenuation reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 30 loudspeaker gain adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 31 line echo cancellation unit - block diagram . . . . . . . . . . . . . . . . . . . .55 figure 32 line echo cancellation unit - superior mode with shadow fir . . . . . .56 figure 33 dtmf detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 34 call progress tone detector - block diagram . . . . . . . . . . . . . . . . . . . .59 figure 35 call progress tone detector- cooked mode . . . . . . . . . . . . . . . . . . . . .59 figure 36 alert tone detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 37 universal tone detector - block diagram . . . . . . . . . . . . . . . . . . . . . . .62 figure 38 caller id decoder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 39 dtmf generator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 40 analog frontend interface - block diagram. . . . . . . . . . . . . . . . . . . . . .67 figure 41 digital interface - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 42 universal attenuator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .69
psb 2170 list of figures page preliminary data sheet 6 10.99 figure 43 automatic gain control unit - block diagram . . . . . . . . . . . . . . . . . . . .70 figure 44 noise reduction - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 45 equalizer - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 46 tone generator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 47 tone generator - tone sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 48 peak detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 49 operation modes - state chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 50 iom ? -2 interface - frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 51 ssdi/iom ? -2 interface - frame start . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 52 iom ? -2 interface - single clock mode . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 53 iom ? -2 interface - double clock mode . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 54 iom ? -2 interface - channel structure. . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 55 ssdi interface - transmitter timing . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 56 ssdi interface - active pulse selection . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 57 ssdi interface - receiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 58 analog front end interface - frame structure. . . . . . . . . . . . . . . . . . . .91 figure 59 analog front end interface - frame start . . . . . . . . . . . . . . . . . . . . . . .92 figure 60 analog front end interface - data transfer. . . . . . . . . . . . . . . . . . . . . .92 figure 61 configuration register read access . . . . . . . . . . . . . . . . . . . . . . . . . . .94 figure 62 configuration register write access or register read command . . . .94 figure 63 status register read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 64 data read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 65 register write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 figure 66 general purpose parallel port - multiplex mode . . . . . . . . . . . . . . . . . .99 figure 67 input/output waveforms for ac-tests . . . . . . . . . . . . . . . . . . . . . . . . .274 figure 68 oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 figure 69 ssdi/iom ? -2 interface - bit synchronization timing . . . . . . . . . . . . . .279 figure 70 ssdi/iom ? -2 interface - frame synchronization timing . . . . . . . . . . .279 figure 71 ssdi interface - strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 figure 72 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 figure 73 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 figure 74 general purpose parallel port - multiplex mode . . . . . . . . . . . . . . . . .284 figure 75 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
psb 2170 list of tables page preliminary data sheet 7 10.99 table 1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 signal summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3 echo cancellation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4 aec mode (qu) encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5 echo cancellation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6 subband mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7 noise reduction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8 speech detector parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9 speech comparator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10 attenuation control parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11 sps encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12 automatic gain control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13 fixed gain parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14 speakerphone registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15 comfort noise generator registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 16 general noise control adaption register. . . . . . . . . . . . . . . . . . . . . . . 50 table 17 correlation adaptation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 18 double talk detection adaptation registers . . . . . . . . . . . . . . . . . . . . 52 table 19 adaptive attenuation reduction registers . . . . . . . . . . . . . . . . . . . . . 53 table 20 loudspeaker gain adaptation registers . . . . . . . . . . . . . . . . . . . . . . . 54 table 44 power down bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 45 sps register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 46 interrupt source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 47 frame synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 48 dependencies of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 49 reprogram parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 50 module weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 51 ssdi vs. iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 52 iom ? -2 interface registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 53 ssdi interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54 control of als amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 55 analog front end interface register . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 56 analog front end interface clock cycles . . . . . . . . . . . . . . . . . . . . . . 92 table 57 command words for register access . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 58 address field w for configuration register write . . . . . . . . . . . . . . . . 97 table 59 address field r for configuration register read . . . . . . . . . . . . . . . . 97 table 60 general purpose parallel port mode registers . . . . . . . . . . . . . . . . . . 98 table 61 static mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 62 multiplex mode registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 63 interrupt mask definition for parallel port . . . . . . . . . . . . . . . . . . . . . 100 table 64 status register update timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
psb 2170 overview preliminary data sheet 8 10.99 1 overview gen era l gen era l the psb 2170, version 2.1 provides a full-duplex speakerphone for analog and digital featurephones. to assure excellent speech quality even in noisy environments like cars, the psb 2170 provides acoustic echo cancellation, comfort noise insertion, and noise reduction adaptive to the environment. depending on the requirements on the runtime delay, this can be performed in fullband or subband mode. furthermore the , version 2.1 features a caller id decoder (bellcore compliant), dtmf recognition and generation and call progress tone detection. the frequency response of cheap microphones or loudspeakers can be corrected by two programmable equalizers. the provides an iom ? -2 compatible interface with up to three channels for speech data. alternatively to the iom ? -2 compatible interface, the supports a simple serial data interface (ssdi) with separate strobe signals for each direction (linear pcm data, one channel). a separate interface is used for a glueless connection to the psb 4851 (dual codec). the chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. the supports interface pins to +5 v input levels.
p-mqfp-80 p r e li m i na r y d a t a s he e t 9 1 0 . 99 acoustic echo canceller ace psb 2170 version 2.1 cmos type package psb 2170 p-mqfp-80 1.1 features two modes of acoustic echo cancellation: 20 db erle 1) @16-80 ms, 0.25-2 ms delay 30 db erle 1) @60-159 ms, 35 ms delay fast adaptation without learning tone two noise reduction blocks comfort noise generator line echo cancellation without learning tone dtmf tone generation flexible ringing generation programmable side gain two transducer correction filters (equalizer) dtmf tone detector call progress tone detector universal tone detector caller id decoder general purpose parallel port (16 bits) independent gain for all channels serial control interface for programming 3.3v power supply, 5v interface iom ? -2 interface (three data channels) interface to psb 4851 interface to burst mode controllers 1) erle: echo return loss enhancement
psb 2170 overview preliminary data sheet 10 10.99 1.2 pin configuration (top view) figure 1 pin configuration 110 20 21 30 40 41 60 50 61 70 80 v dda xtal 1 xtal 2 ri ro v ssa sclk sdr v dd afedd afedu v dd v ss v dd v ss afefs afeclk fsc du/dx dd/dr dxst drst v dd v ss dcl ro ri ro ro ro sps 0 sps 1 v dd v ss ri ri gp 3 gp 2 gp 1 gp 0 ri ri ri ri ri v dd v ss v dd v ss v ss v ss ro v dd gp 4 gp 5 gp 6 v dd gp 8 v ss gp 15 v ss gp 7 gp 9 gp 10 v dd gp 12 gp 13 gp 14 v ss gp 11 nc rst clk v ss ri nc int sdx cs ro ace
psb 2170 overview preliminary data sheet 11 10.99 1.3 pin definitions and functions table 1 pin definitions and functions pin no. p-mqfp-80 symbol dir. 1) reset function 7, 15, 21, 29, 39, 49, 58, 61, 67, 73 v dd -- power supply (3.3v % ) power supply for logic. 1 v dda -- power supply (3.3v %) power supply for clock generator. 4 v ssa -- power supply (0 v) ground for clock generator. 9, 16, 22, 30, 40, 48, 57, 59, 60, 78, 66, 72 v ss -- power supply (0 v) ground for logic and interface. 17 afefs o l analog frontend frame sync: 8 khz frame synchronization signal for communication with the analog frontend. 18 afeclk o l analog frontend clock: clock signal for the analog frontend (6.912 mhz). 19 afedd o l analog frontend data downstream: data output to the analog frontend. 20 afedu i - analog frontend data upstream: data input from the analog frontend. 79 rst i - reset: active high reset signal. 23 fsc i - data frame synchronization: 8 khz frame synchronization signal (iom ? -2 and ssdi mode). 24 dcl i - data clock: data clock of the serial data of the iom ? -2 compatible and the ssdi interface. 5 5
psb 2170 overview preliminary data sheet 12 10.99 26 dd/dr i /od i - iom ? -2 compatible mode: receive data from iom ? -2 controlling device. ssdi mode: receive data of the strobed serial data interface. 25 du/dx i /od o/ od - iom ? -2 compatible mode: transmit data to iom ? -2 controlling device. ssdi mode: transmit data of the strobed serial data interface. 27 dxst o l dx strobe: strobe for dx in ssdi interface mode. 28 drst i - dr strobe: strobe for dr in ssdi interface mode. 14 cs i- chip select: select signal of the serial control interface (sci). 11 sclk i - serial clock: clock signal of the serial control interface (sci). 13 sdr i - serial data receive: data input of the serial control interface (sci). 12 sdx o/ od h serial data transmit: data output of the serial control interface (sci). 10 int o/ od h interrupt new status available. 8clki- alternative afeclk source 13,824 mhz 2 3 xtal 1 xtal 2 i o - z oscillator: xtal 1 : external clock or input of oscillator loop. xtal 2 : output of oscillator loop for crystal. 37 38 sps 0 sps 1 o o l l speakerphone state: current speakerphone unit state, general purpose outputs or status register output table 1 pin definitions and functions
psb 2170 overview preliminary data sheet 13 10.99 52 53 54 55 62 63 64 65 68 69 70 71 74 75 76 77 gp 0 gp 1 gp 2 gp 3 gp 4 gp 5 gp 6 gp 7 gp 8 gp 9 gp 10 gp 11 gp 12 gp 13 gp 14 gp 15 i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) general purpose parallel port 0-15: general purpose i/o. 6, 32, 33, 34, 35, 36, 56 ro o - reserved output: do not connect. 5, 31, 42, 43, 44, 45, 46, 47, 50, 51 ri i - reserved input: connect to v ss . 41, 80 nc - - not connected 1) i = input o = output od = open drain 2) these lines are driven low with 102 a (typical) during reset. table 1 pin definitions and functions
psb 2170 overview preliminary data sheet 14 10.99 1.4 logic symbol 1 figure 2 logic symbol du/dx dd/dr dcl fsc sdx sdr sclk cs iom ? -2 sci afeclk afefs afedu afedd psb psb 2170 xtal 1 xtal 2 rst ssdi 4851 dxst drst parallel port gp 0 -gp 15 int
psb 2170 overview preliminary data sheet 15 10.99 1.5 functional block diagram figure 3 psb 2170 - block diagram du/dx dd/dr dcl fsc sdx sdr sclk cs afeclk afefs afedu afedd xtal 1 xtal 2 rst dsp reset and timing unit data interface analog frontend interface dxst drst control interface parallel port gp 0 -gp 15 int
psb 2170 overview preliminary data sheet 16 10.99 1.6 system integration the psb 2170 provides a full-duplex speakerphone in a variety of applications. some applications are given in the following sections. 1.6.1 full-duplex speakerphone for isdn terminal figure 4 shows an example of an isdn featurephone with the psb 2170 providing a full- duplex speakerphone. figure 4 full-duplex featurephone for isdn terminal ace microcontroller 077-3445 iom ? -2 s 0 -bus power controller peb 2023 scout-s sci psb 2170 psb 21381
psb 2170 overview preliminary data sheet 17 10.99 1.6.2 full-duplex speakerphone for pbx terminal figure 5 shows an example of a pbx phone with the psb 2170 providing a full-duplex speakerphone. figure 5 full-duplex featurephone for pbx terminal ace microcontroller 077-3445 iom ? -2 u pn -bus dc/dc converter scout-p sci psb 2170 psb 21381
psb 2170 overview preliminary data sheet 18 10.99 1.6.3 dect basestation with full-duplex speakerphone figure 6 shows a dect basestation with acoustic echo cancellation based on the psb 2170. the full-duplex speakerphone can be switched to the basestation or a mobile handset dynamically. for programming, the serial control interface (sci) is used while voice data is transferred via the strobed serial data interface (ssdi). figure 6 dect basestation with full-duplex speakerphone ace sam afe microcontroller 077-3445 antenna burstmode controller dect hf line tip/ ring afe sci iom ? -2/ssdi psb 4851 psb 2170
psb 2170 overview preliminary data sheet 19 10.99 1.6.4 videophone with external line interface a videophone using an external line interface with the psb 2170 providing a full-duplex speakerphone is shown in figure 7. figure 7 videophone with external line interface (hardware video codec) in transmit direction the psb 2161 (arcofi ba) provides the uncompressed audio data from the microphone to the acoustic echo canceller (psb 2170). the acoustic echo canceller provides the echo-free data to the audio compression device jade mm (psb 7238). the jade mm offers all necessary compression algorithms to cover h.320/323/ 324 applications, i.e. itu-t g.711, g.722, g.723 and g.728. the compressed data is then multiplexed into the audio/video data stream by the video codec. the video codec in turn sends the combined data via the bus interface to a host unit (e.g. the cpu in a pc) which passes it to the line interface (e.g. isac-s te for isdn, v.34bis modem for pots or an ethernet adapter for lan). in receive direction the same signal path is used in the other direction. the off-board line interface offers the advantage of one videophone board applicable to different lines such as isdn (h.320), lan (h.323) or pots (h.324, plain old telephone system) by just exchanging the line interface card and some control software on the pc. iom ? -2 video codec bus interface arcofi ba psb 2161 ace psb 2170 jade mm psb 7238
psb 2170 overview preliminary data sheet 20 10.99 1.6.5 videophone with software video compression a videophone using software video compression with the psb 2170 providing a full- duplex speakerphone is shown in figure 8. figure 8 videophone with external line interface (software video codec) in transmit direction the psb 2161 (arcofi ba) provides the uncompressed audio data from the microphone to the acoustic echo canceller (psb 2170). the acoustic echo canceller provides the echo-free data to the audio compression device jade mm (psb 7238). the jade mm offers all necessary compression algorithms to cover h.320/323/ 324 applications, i.e. itu-t g.711, g.722, g.723 and g.728. the compressed data is then transmitted to the host processor via the bus interface (e.g. using the pci interface szb 6120). the host processor also captures the uncompressed video data through the same bus interface and does the video compression and multiplexing by software. the multiplexed data stream is then passed to the corresponding line interface (e.g. isac-s te for isdn, v.34bis modem for pots or an ethernet adapter for lan). in receive direction the same signal path is used in the other direction. if only h.324 (pots) videophones shall be supported, the jade mm (psb 7238) may be substituted by the jade an (psb 7230), which offers only the itu-t g.723.1 compression needed for h.324. a combi-design of jade mm and jade an is also possible, thus offering both solutions by assembly options. see jade an data sheet for details. iom ? -2 bus interface arcofi ba psb 2161 ace psb 2170 jade mm psb 7238 szb 6120
psb 2170 overview preliminary data sheet 21 10.99 the off-board line interface offers the advantage of one videophone board applicable to different lines such as isdn (h.320), lan (h.323) or pots (h.324, plain old telephone system) by just exchanging the line interface card and some control software on the pc. due to the limited computational power of the host processor (e.g. intel pentium), the video quality using software compression usually does not reach the quality of a separate video processor. nevertheless, if accepted by the customer this offers a very low cost solution for videoconferencing. 1.6.6 full-duplex speakerphone in car environment the has several special provisions for operation in noisy environments like cars. most important are two noise reduction blocks. one is built in the transmit path of the speakerphone. the other one is a free module that can be inserted into any path. figure 9 shows an application where the provides a full-duplex speakerphone for a mobile communications unit in a car. figure 9 full-duplex speakerphone in car environment the receives (transmits) analog data from (to) the mobile communications unit via the first codec of the psb 4851. the microphone and the loudspeaker of the mobile communications unit are muted. instead of them the loudspeaker and microphone mounted in the car are used. they are connected directly to the second channel of the psb 4851. c psb 4851 psb 2170 sci
psb 2170 overview preliminary data sheet 22 10.99 1.7 backward compatibility the psb 2170 version 2.1 is backwards compatible with the psb 2170 version 1.1 with respect to: pin configuration supply voltage signal levels start-up sequence after reset register definition of all modules with exception of the speakerphone the speakerphone has significantly changed and improved. some registers have become obsolete, others have been added. therefore, not all registers of the speakerphone are compatible to the psb 2170 version 1.1. all of the other additional features of the psb 2170 version 2.1 are enabled by previously unused bits of the hardware configuration registers or the read/write registers or by additional registers. furthermore, the status bits are updated faster which should have no impact on backwards compatibility.
psb 2170 functional units preliminary data sheet 23 10.99 2 functional units functional units functional units the psb 2170 contains several functional units that can be combined with almost no restrictions to perform a given task. figure 10 shows the functional units available within the ace. figure 10 functional units - overview dtmf detector speaker- phone cid decoder psb 4851 ssdi/iom ? -2 iom ? -2 s 1 s 3 s 5 s 7 s 11 s 12 s 4 s 2 s 8 s 6 signal summation: signal sources: s 1 ,...,s 21 channel 1 i 1 i 2 i 3 line side acoustic side sci i 1 i 1 i 2 i 3 i 1 i 2 i 3 channel 2 channel 1 i 3 i 4 i 1 i 2 i 1 i 2 i 3 i 1 i 2 i 3 i 1 alert tone detector i 1 line echo canceller i 2 s 15 equalizer 2 i 1 s 19 psb 4851 channel 2 equalizer 1 i 1 s 18 tone s 20 universal i 1 s 14 attenuator generator dtmf s 9 generator s 10 cpt detector i 1 s 21 noise i 1 s 25 reduction agc i 1 i 2 s 17 s 16 i 1 iom ? -2 s 23 s 24 channel 3 i 1 i 2 i 3 utd detector i 1
psb 2170 functional units preliminary data sheet 24 10.99 each unit has one or more signal inputs (denoted by i). most units have at least one signal output (denoted by s). any input i can be connected to any signal output s. in addition to the signals shown in figure 10 there is also the signal s 0 (silence), which is useful at signal summation points. table 2 lists the available signals within the according to their reference points. table 2 signal summary signal description s 0 silence s 1 analog line input (channel 1 of psb 4851 interface) s 2 analog line output (channel 1 of psb 4851 interface) s 3 microphone input (channel 2 of psb 4851 interface) s 4 loudspeaker/handset output (channel 2 of psb 4851 interface) s 5 serial interface input, channel 1 s 6 serial interface output, channel 1 s 7 serial interface input, channel 2 s 8 serial interface output, channel 2 s 9 dtmf generator output s 10 dtmf generator auxiliary output s 11 speakerphone output (acoustic side) s 12 speakerphone output (line side) s 13 reserved s 14 universal attenuator output s 15 line echo canceller output s 16 automatic gain control output (after gain stage) s 17 automatic gain control output (before gain stage) s 18 equalizer 1 output s 19 equalizer 2 output s 20 tone generator output 1 s 21 tone generator output 2 s 22 reserved s 23 serial interface input, channel 3 s 24 serial interface output, channel 3 s 25 nr output
psb 2170 functional units preliminary data sheet 25 10.99 the following sections describe the functional units in detail. figure 11 gives an example of how the units may be combined when a hands-free phone conversation is in progress. units that are not needed are not shown. unused inputs are connected to s 0 which provides silence (denoted as 0). the equalizers are used to improve the quality of the microphone and the loudspeaker. the alert tone detector recognizes an alert tone of an off-hook caller id request while the cid decoder then decodes the actually transmitted data. figure 11 functional units - speakerphone speaker- phone cid decoder loud- micro- 0 line side acoustic side sci alert tone detector line echo canceller equalizer 2 line line equalizer 1 phone speaker in out 0 0 0 0 0
psb 2170 functional units preliminary data sheet 26 10.99 2.1 full-duplex speakerphone the speakerphone unit (figure 12) is attached to four signals (microphone, loudspeaker, line out and line in). the two input signals (microphone, line in) are preceded by a signal summation point. figure 12 speakerphone - signal connections internally, this unit can be divided into an echo cancellation unit and an echo suppression unit (figure 13). the echo cancellation unit provides the attenuation g c while the echo suppression unit provides the attenuation g s . the total attenuation att of the speakerphone is therefore att=g c +g s . figure 13 speakerphone - block diagram the echo cancellation unit estimates that part of the signal at the microphone that originates from the loudspeaker. this part is then subtracted from the signal at the microphone. this technique allows a full-duplex speakerphone. furthermore, the echo cancellation unit has a built-in noise reduction unit for better sound quality at the line side. the echo suppression unit attenuates the receive or transmit path dependent on what path is active. without the echo cancellation unit and by using a high attenuation of the echo suppression unit, the echo suppression unit provides a half-duplex speakerphone. speakerphone s 11 s 12 a c o u s t i c s i d e l i n e s i d e i 2 i 1 i 3 i 4 microphone loudspeaker line out line in echo cancellation line out microphone loudspeaker line in echo suppression g c g s functional units.
psb 2170 functional units preliminary data sheet 27 10.99 if the echo cancellation unit is active but cannot provide all of the required attenuation itself, the echo suppression unit can be used to provide additional attenuation. 2.1.1 echo cancellation unit the echo cancellation unit has two operating modes: fullband and subband mode. table 3 shows the basic differences of the two modes. the selection between the modes is performed with the parameter qu as summarized in table 4. the different modi are described in the sequel. table 3 echo cancellation modes fullband mode subband mode max. g c 20 db 30 db echo length 16-80 ms 50-159 ms delay 0.25-2 ms 35 ms table 4 aec mode (qu) encoding qu 2 qu 1 qu 0 acoustic echo cancellation modes 0 0 0 echo cancellation disabled (half duplex) 0 0 1 subband, rnr 0 1 0 fullband mode one (similar to psb 2170 version 1.1) 0 1 1 fullband mode two 1 0 0 subband, reduced filter length (car kit application) 1 0 1 subband, analog line mode 1 1 0 subband, isdn mode 1 1 1 subband, enhanced mode
psb 2170 functional units preliminary data sheet 28 10.99 2.1.1.1 echo cancellation (fullband mode) a simplified block diagram of the fullband echo cancellation unit is shown in figure 14. figure 14 echo cancellation unit (fullband mode) - block diagram the echo cancellation unit consists of a finite impulse response filter (fir) that models the expected acoustic echo, an nlms based adaptation unit and a control unit. the expected echo is subtracted from the actual input signal from the microphone. if the model is exact and the echo does not exceed the length of the filter, then the echo can be cancelled completely. however, even if this ideal state can be achieved for one given moment, the acoustic echo usually changes over the time. therefore the nlms unit continuously adapts the coefficients of the fir filter. this adaptation process is steered by the control unit. as an example, the adaptation is inhibited as long as double talk is detected by the control unit. furthermore the control unit informs the echo suppression unit about the achieved echo return loss. the length of the fir can be programmed by the parameters fblen. with the parameter qu, the echo cancellation unit can be set into two different fullband modes (section 2.1.1). the fullband mode one is similar to the mode provided in the psb 2170 version 1.1. in this mode, the noise reduction (chapter 2.1.2) cannot be enabled. the delay added in this mode is 0.25 ms. in the fullband mode two, the delay is shorter than 2 ms. if this delay is not acceptable, the delay can be reduced to less than 1 ms by setting the bit erd. the performance of the fullband mode may suffer in this reduced mode but please note that enabling the noise reduction will add some additional delay (section 2.1.2). microphone loudspeaker - fir filter nlms control line out line in
psb 2170 functional units preliminary data sheet 29 10.99 in order to detect double talk, the remaining speech signal after the echo cancellation (signal after summation point in figure 14) is compared to the signal expected by the echo cancellation unit (after the signal summation point in figure 14). the difference of the energy of these signals is considered. if this energy is greater than allowed by the parameter aecdtm, double talk is detected. when double talk is detected, the attenuation of the echo cancellation is reduced since the echo is less noticeable anyway and any possible signal distortion from the echo cancellation is reduced. the parameter aecdtr determines the maximal reduction of the attenuation during double talk. the rate how fast the attenuation reduction gets active after double talk detection or inactive after the end of double talk is determined by the parameters aecdti and aecdtd, respectively. figure 15 echo cancellation unit - double talk reduction the echo cancellation unit reports its current attenuation to the echo suppression unit. this has the following reason: if the echo cancellation does not provide enough attenuation, the echo suppression can be used additionally. the attenuation of the echo cancellation unit may be insufficient when the echo cancellation unit is not yet well adapted. in case of a significant change of the characteristics of the acoustics, the attenuation reported by the echo cancellation unit may be too high until it discovers that it has to adapt itself again. if, in addition, double talk reduction is in effect, then the echo suppression unit might not attenuate enough to avoid echoes. therefore a maximal echo return loss reported by the echo cancellation unit to the echo suppression unit can be programmed by the parameter aeclim. in fullband mode two, the number of fir parameters that are adapted every 125 us can be programmed by the parameter fbada. the maximum number of taps that get their parameters adapted is 256. if for example the number of taps used by the fir is 512 and -30 db aecdtr time aec attenuation level -10 db -20 db double end of example: talk detected a e c dt i a e c d t d double talk
psb 2170 functional units preliminary data sheet 30 10.99 fbada is 256, the parameters of the lower 256 taps and of the upper 256 taps get updated alternately. the value of fbada has therefore the following two effects: first, the higher fbada the faster the fir and thus the echo canceller is adapted. second, with increasing fbada, the comutational costs increase. if affordable from the computational costs (see chapter 3.7), fbada should be set to its maximum value. table 5 shows the registers associated with the echo cancellation unit in fullband mode. the length of the fir filter for the echo compensation can be varied from 63 up to 542 taps (~68 ms) if comfort noise (chapter 2.1.4) is enabled 639 taps (~80 ms) if fullband mode one is used and comfort noise is disabled 645 taps (~80 ms) if fullband mode two is used and comfort noise is disabled 768 taps (~96 ms) if fullband mode two is used and the same module as in subband isdn mode are disabled (chapter 3.7). the length of the adaption window can be varied from 64 to 256 taps (8 ms to 32 ms). table 5 echo cancellation unit registers register # of bits name comment sctl 3 qu determine aec modes (see table 4) sctl 1 erd enable reduced delay for new fullband mode. saelen 10 fblen length of fir filter. saeaw 9 fbada length of adaption window. (fb mode two only) saeel 15 aeclim maximum attenuation reported by the aec unit. saedtr 15 aecdtr aec attenuation reduction during double-talk. saedtl 15 aecdtm minimum energy to detect double talk. saedti 15 aecdti how fast the attenuation reduction gets incremented. saedtd 15 aecdtd how fast the attenuation reduction gets decremented.
psb 2170 functional units preliminary data sheet 31 10.99 2.1.1.2 echo cancellation (subband mode) a simplified block diagram of the subband echo cancellation unit is shown in figure 16. the signal coming from the microphone and the signal from the line side are analyzed into several subbands. then for each subband, the block diagram of figure 16 is identical to the block diagram of the fullband mode. after the echo cancellation of each subband, the subbands are synthesized. finally and additionally to the fullband mode, in the subband mode an optional wiener filter (called wf in figure 16) is provided. figure 16 echo cancellation unit (subband mode) - block diagram the subband mode can be enabled in five different submodes. these submodes offer a trade-off between the maximum echo length and the functional units that can be run simultaneously (see chapter 3.7). all units that cannot be run simultaneously must be disabled before the subband echo cancellation unit is enabled. after the subband echo cancellation unit is disabled, the parameters for the affected units must be rewritten by the microcontroller. for the optional wiener filter, the maximum attenuation can be programmed with the parameter wfatt. if the wiener filter is enabled, it is only active while there is no speech detected on the near side (microphone). as shown in figure 13 the total attenuation provided by the speakerphone consists of the attenuation g c (provided by the echo cancellation unit) and g s (provided by the echo suppression unit). in subband mode the attenuation g c is further split into g a (provided by the adaptive filter) and g w (provided by the wiener filter). micro- loudspeaker - fir filter nlms control line line in wf analysis analysis phone out synthesis
psb 2170 functional units preliminary data sheet 32 10.99 if g a already exceeds wfatt due to good adaptation then the wiener filter is deactivated and g c =g a . otherwise wfatt limits the attenuation g w of the wiener filter such that g c =g a +g w never exceeds wfatt. table 6 shows the registers associated with the subband echo cancellation unit. the parameters aecatt, aeclim, aecdtm, aecdti and aecdtd have the same meaning as in fullband mode. note that the reported echo loss and parameter aeclim cover the complete echo cancellation unit including the wiener filter. as shown in table 4, with the control bits qu different modes of the acoustic echo cancellation unit can be selected. in subband mode, four different modes are provided. with increasing number of qu, the considered echo length increases and so does the computational effort. before selecting a mode, the incompatibilities described in chapter 3.7 must be considered. 2.1.2 noise reduction the psb 2170 offers a noise reduction block built in the echo cancellation unit. this noise reduction suppresses noise before the signal is output to the line side. this makes conversation more pleasant for the person at the line side. in fullband mode, the noise reduction can only be enabled if the fullband mode two is used. the noise reduction is performed after the echo cancellation and can thus be considered as an additional block after the echo cancellation as shown in figure 14. note that the noise reduction adds about 1 ms delay to the signal. if the bit sctl:erd is set, then the delay for echo cancellation and noise reduction is st ill below 2 ms. in subband mode, the noise suppression is performed for each subband. figure 16 shows how the noise reduction block (called nr) matches in the echo cancellation unit. the noise reduction adds no delay to the signal. table 6 subband mode registers register # of bits name comment sctl 3 qu determine aec modes sctl 1 ewf wiener filter enable (subband only) saewfl 15 wfatt wiener filter attenuation limit saedtr 15 aecatt aec attenuation reduction during double-talk saeel 15 aeclim upper limit of the attenuation of the aec saedtl 15 aecdtm minimum energy to detect double talk saedti 15 aecdti how fast the attenuation gets incremented. saedtd 15 aecdtd how fast the attenuation gets decremented.
psb 2170 functional units preliminary data sheet 33 10.99 figure 17 echo cancellation with noise reduction (subband mode) the parameter nratt determines the maximum attenuation provided by the noise reduction unit for frequencies with noise. note that nratt determines a upper limit. with decreasing level of the background noise, the attenuation of the noise reduction unit decreases as well. in subband mode, if the wiener filter is enabled and if no speech is detected at the microphone, the wiener filter provides attenuation of the signal from the microphone. if noise is present at the microphone and thus the noise reduction unit changes the signal coming from the microphone, then the additional attenuation of the wiener filter can cause modulations audible at the line side. therefore, a coupling of the noise reduction unit and the wiener filter is provided. in case no noise is present at the near end, the wiener filter attenuates as programmed with the parameter swatt:wfatt. in case significant noise is present at the near end, the wiener filter only attenuates so much that the attenuation of the noise reduction plus the attenuation of the wiener filter never exceeds nratt. this is controlled with two parameters: the parameter nrup determines the noise energy at which the coupling between the noise reduction and the wiener filter gets active. the parameter nrlow determines the noise energy at which the coupling gets inactive. this value should be lower than nrup in order to avoid frequent activation and deactivation, when the noise energy is around the level of nrup as illustrated in figure 18. micro- loudspeaker - fir filter nlms control line line in wf analysis analysis phone out synthesis nr
psb 2170 functional units preliminary data sheet 34 10.99 figure 18 coupling nr with wf 2.1.3 echo suppression the echo suppression unit can be in one of three states: transmit state receive state idle state in transmit state the microphone signal drives the line output while the line input is attenuated. in receive state the loudspeaker signal is driven by the line input while the microphone signal is attenuated. in idle state both signal paths are active with evenly distributed attenuation. table 7 noise reduction registers register # of bits name comment sctl 1 nr enable noise reduction snratt 15 nratt maximal attenuation of frequencies with noise. snrlnl 15 nrlow lower limit to deactivate coupling. snrunl 15 nrup upper limit to activate coupling. nrup time noise level background nr-wf coupling start nr-wf coupling end nrlow
psb 2170 functional units preliminary data sheet 35 10.99 figure 19 echo suppression unit - states of operation line out line in microphone loudspeaker idle state line out line in microphone loudspeaker receive state line out line in microphone loudspeaker transmit state
psb 2170 functional units preliminary data sheet 36 10.99 figure 20 shows the signal flow graph of the echo suppression unit in more detail. figure 20 echo suppression unit - block diagram the attenuation control performs the switching between the three possible states by using the attenuation stages ghx and ghr. actually, state switching is controlled by the speech comparators scas and scls and by the speech detectors sdx and sdr. the gain control units agcx, agcr, lgax, and lgar are used to achieve proper signal levels for each state. all blocks are programmable. thus, the telephone set can be optimized and adjusted to the particular geometrical and acoustical environment. the following sections discuss the blocks of the echo suppression unit in detail. scls scas sdx sdr agcr agcx attenuation control line out microphone loudspeaker lgax lgar line in ghx ghr
psb 2170 functional units preliminary data sheet 37 10.99 2.1.3.1 speech detector for each signal source a speech detector (sdx, sdr) is available. the speech detectors are identical but can be programmed individually. figure 21 shows the signal flow graph of a speech detector. figure 21 speech detector - block diagram the first three units (lim, lp1, pd) are used for preprocessing the signal while the actual speech detection is performed by the background noise monitor. background noise monitor the tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. therefore the background noise monitor consists of the low-pass filter 2 (lp2) and the offset in two separate branches. basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). in contrast, background noise can be regarded approximately stationary from its average power. low-pass filter 2 provides different time constants for noise (non-detected speech) and speech. it determines the average of the noise reference level. in case of background noise the level at the output of lp2 is approximately the level of the input. as in the other branch an additional offset off is added to the signal, the comparator signals noise. at speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the lp2-branch. if the difference exceeds the offset off, the lim lp1 pd lp2 off lp1 pds pdn lp2s lp2n lp2l background noise monitor signal preprocessing - lim
psb 2170 functional units preliminary data sheet 38 10.99 comparator signals speech. therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). a small fade constant (lp2n) enables fast settling of lp2 to the average noise level after the end of speech recognition. however, a too small time constant for lp2n can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. it is recommended to choose a large rising constant (lp2s) so that speech itself charges the lp2 very slowly. generally, it is not recommended to choose an infinite lp2s because then approaching the noise level is disabled. during continuous speech or tones the lp2 will be charged until the limitation lp2l is reached. then the value of lp2 is frozen until a break discharges the lp2. this limitation permits transmission of continuous tones and ? music on hold ? . the offset stage represents the estimated difference between the speech signal and averaged noise. signal preprocessing as described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. in very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. therefore a peak detection is required in front of the noise monitor. the main task of the peak detector (pd) is to bridge the very short speech pauses during a monolog so that this time constant has to be long. furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. but if no speech is recognized the noise low-pass lp2 must be charged faster to the average noise level. in addition, the noise edges are to be smoothed. therefore two time constants are necessary. as the peak detector is very sensitive to spikes, the low-pass lp1 filters the incoming signal containing noise in a way that main spikes are eliminated. due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. to compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. the limitation of the logarithmic amplifier can be programmed via the parameter lim. lim is related to the maximum pcm level. a signal exceeding the limitation defined by lim is getting amplified logarithmically, while very smooth system noise below is neglected. it should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path. table 8 shows the parameters for the speech detector.
psb 2170 functional units preliminary data sheet 39 10.99 the input signal of the speech detector can be connected to either the input signal of the echo suppression unit (as shown for sdx) or the output of the associated agc (as shown for sdr). table 8 speech detector parameters parameter # of bytes range comment lim 1 0 to -95 db limitation of log. amplifier off 1 0 to 95 db level offset up to detected noise pds 1 1 to 2000 ms peak decrement pd1 (speech) pdn 1 1 to 2000 ms peak decrement pd1 (noise) lp1 1 1 to 2000 ms time constant lp1 lp2s 1 2 to 250 s time constant lp2 (speech) lp2n 1 1 to 2000 ms time constant lp2 (noise) lp2l 1 0 to 95 db maximum value of lp2
psb 2170 functional units preliminary data sheet 40 10.99 2.1.3.2 speech comparators (sc) the echo suppression unit has two identical speech comparators (scas, scls). each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. as scas and scls are identical, the following description holds for both scas and scls. the sc has two input signals sx and sr, which map to microphone/loudspeaker for scas and line in/line out for scls. the speech comparator decides whether the signal coming in on sr is only an echo from the signal outgoing on sx or a real speech activity. the result is then interpreted by the attenuation control of figure 20. in general, the sc works according to the following equation: therefore, scas controls the switching to transmit state and scls controls the switching to receive state. switching is done only if sx exceeds sr by at least the expected acoustic level enhancement v. this level enhancement is divided into two parts: g and gd. a block diagram of the sc is shown in figure 22. figure 22 speech comparator - block diagram at both inputs, logarithmic amplifiers compress the signal range. hence, only logarithmic levels are on both paths and after the signals have been processed, logarithmic levels on both paths are compared. if sx > sr + v then switch state g gds gdn pds pdn sx sr log. amp. base gain gain reserve peak decrement log. amp. pds pdn peak decrement
psb 2170 functional units preliminary data sheet 41 10.99 the main task of the comparator is to control the echo. the internal coupling due to the direct sound and mechanical resonances is covered by g. the external coupling, mainly caused by the acoustic feedback, is controlled by gd/pd. an example for direct sound (1) and acoustic feedback (2) is illustrated in figure 23. figure 23 speech comparator - acoustic echoes the base gain g corresponds to the terminal couplings of the complete telephone. thus, g is the measured or calculated level enhancement between the receive and the transmit inputs of the sc. to control the acoustic feedback two parameters are necessary: gd represents the actual reserve on the measured g. together with the peak decrement (pd), the echo behavior at the acoustic side is modeled: after speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. till the end of that time ( ? t ), the level enhancement v must be at least equal to g to prevent clipping caused by these internal couplings. after that time ( ? t ), only the acoustic feedback is present. this coupling, however, is reduced by air attenuation. for this in general the longer the delay, the smaller the echo being valid. this echo behavior is taken care of by the decrement rate pd. 1 2
psb 2170 functional units preliminary data sheet 42 10.99 figure 24 speech comparator - interdependence of parameters according to figure 24, a compromise between the reserve gd and the decrement pd has to be made: a smaller reserve (gd) above the level enhancement g requires a longer time to decrease (pd). it is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. in contrary, with a higher reserve (gd*) it is harder to overshout continuous speech or tones, but it enables a faster intercommunication because of a stronger decrement (pd*). two pairs of coefficients, gds/pds when speech is detected, and gdn/pdn in case of noise, offer a different echo handling for speech and non-speech. with speech, even if very strong resonances are present, the performance w ill not be worsened by the high gds needed. only when speech is detected, a high reserve prevents clipping. the time et [ms] after speech ends, the parameters of the comparator are switched to the ? noise ? values. if both sets of the parameters are equal, et has no effect. table 9 speech comparator parameters parameter # of bytes range comment g1 ? 48 to + 48 db base gain gds 1 0 to 48 db gain reserve (speech) pds 1 0.025 to 6 db/ms peak decrement (speech) t db ? t gd* gd pd* pd rx-speech rx-noise g g
psb 2170 functional units preliminary data sheet 43 10.99 2.1.3.3 attenuation control the attenuation control unit performs state switching by controlling the attenuation stages ghx and ghr. in receive state, the attenuation g is completely switched to ghx. in transmit state, the attenuation g is completely switched to ghr. in idle state, both ghx and ghr attenuate by g/2. state switching depends on the signals of one speech comparator and the corresponding speech detector. the attenuation g is programmable. the attenuation g actually provided by the attenuation stages ghr and ghx is the attenuation determined by the parameter att minus the attenuation reported by the echo cancellation unit (g = att - g c ). additional (fixed) attenuation on the transmit and receive path is also influenced by the automatic gain control stages agcx and agcr, respectively. while each state is associated with the programmed attenuation, the time t sw it takes to reach the steady-state attenuation after a state switch can be programmed. the time t sw depends on a programmable decay rate sw and the current attenuation g by the formula . if the current state is either transmit or receive and no speech on either side has been detected for time t tw then the idle state is entered. to smoothen the transition, the attenuation is incremented (decremented) by ds until the evenly distribution g/2 for both ghx and ghr is reached. table 10 summarizes the parameters for the attenuation unit. note: in addition, attenuation is also influenced by the automatic gain control stages (agcx, agcr) in order to keep the total loop attenuation constant. gdn 1 0 to 48 db gain reserve (noise) pdn 1 0.025 to 6 db/ms peak decrement (noise) et 1 0 to 992 ms time to switch from speech to noise parameters table 10 attenuation control parameters parameter # of bytes range comment tw 1 16 ms to 4 s t tw to return to idle state att 1 0 to 95 db attenuation for ghx and ghr ds 1 0.6 to 680 ms/db decay speed (to idle state) sw 1 0.0052 to 10 ms/db decay rate (used for t sw ) table 9 speech comparator parameters parameter # of bytes range comment t sw sw g =
psb 2170 functional units preliminary data sheet 44 10.99 note: by programming parameter ds to 0xff idle mode is disabled and the speakerphone will remain in the last state. this parameter must be set before enabling the speakerphone. 2.1.3.4 echo suppression status output the psb 2170 can report the current state of the echo suppression unit to ease the optimization of the parameter set of the echo suppression unit. in this case the sps 0 and sps 1 pins are set according to table 11. furthermore the controller can read the current value of the sps pins by reading register spsctl. 2.1.3.5 loudhearing the speakerphone unit can also be used for controlled loud-hearing. this is enabled by setting bit md in register sctl. if loud-hearing mode is enabled, the loudspeaker amplifier of the psb 4851 (als) is used instead of ghr (figure 20) when appropriate to avoid oscillation. to use this feature, the psb 4851 must be programmed to allow als override. the als field within the afe control register afectl defines the value sent to the psb 4851 if attenuation is necessary (see specification of the psb 4851). 2.1.3.6 automatic gain control the echo suppression unit has two identical automatic gain control units agcx and agcr both referred to as agc in this section. whether the automatic gain control agc amplifies or attenuates depends on whether the signal level is above or below the threshold level defined by parameter com. the threshold is relative to the maximum pcm-value and thus negative. the parameters ag_gain and ag_att determine the maximal amplification and attenuation, respectively. the bold line in figure 25 gives an example for the steady-state output level of the agc as a function of the input level. table 11 sps encoding sps 0 sps 1 echo suppression unit state 0 0 no echo suppression operation 01receive 10transmit 1 1 idle
psb 2170 functional units preliminary data sheet 45 10.99 figure 25 echo suppression unit - automatic gain control for reasons of physiological acceptance, the agc gain is automatically reduced in case of continuous background noise (e.g. by ventilators). the reduction is programmed via the nols parameter. when the noise level exceeds the threshold determined by nois, the amplification will be reduced by the same amount the noise level is greater than the threshold. the regulation speed is controlled by speedh for signal amplitudes above the threshold and speedl for amplitudes below. usually speedh will be chosen to be at least 10 times faster than speedl. an additional low pass with time constant lp is provided to avoid an immediate response of the agc to very short signal bursts. the time constant of the low pass should not be selected longer than 4 ms in order to avoid unstable behavior. if the speech detector sdx detects noise or the receive path is active, agcx freezes its current attenuation and the last gain setting is used. regulation starts with this value as soon as sdx detects speech and the receive path is inactive. likewise, if sdr detects noise or the transmit path is active, agcr freezes its current attenuation and the last gain setting is used. regulation starts with this value as soon as sdr detects speech and the transmit path is inactive. the current gain/attenuation of the agc can be read at any time (ag_cur). when the agc has been disabled, the initial gain used immediately after enabling the agc can be programmed. table 12 shows the parameters of the agc. com ag_att ag_gain agc input level agc output level max. pcm -10 db -20 db -10 db -20 db example: com ag_gain ag_att = = = -30 db 15 db 20 db
psb 2170 functional units preliminary data sheet 46 10.99 note: there are two sets of parameters, one for agcx and one for agcr. note: by setting ag_gain to 0 db a limitation function can be realized with the agc. 2.1.3.7 fixed gain each signal path features an additional amplifier (lgax, lgar) that can be set to a fixed gain. these amplifiers should be used for the basic amplification in order to avoid saturation in the preceding stages. table 13 shows the only parameter of this stage. 2.1.3.8 mode control table 14 shows the registers used to determine the signal sources and the mode. table 12 automatic gain control parameters parameter # of bytes range comment ag_init 1 -95 db to 95db initial agc gain/attenuation com 1 0 to ? 95 db compare level rel. to max. pcm-value ag_att 1 0 to -95 db attenuation range ag_gain 1 0 to 95 db gain range ag_cur 1 -95 db to 95 db current gain/attenuation speedl 1 0.25 to 62.5 db/s change rate for lower levels speedh 1 0.25 to 62.5 db/s change rate for higher levels nois 1 0 to ? 95 db threshold for agc-reduction by background noise lpa 1 0.025 to 4 ms agc low pass time constant table 13 fixed gain parameters parameter # of bytes range comment lga 1 -12 db to 12 db always active table 14 speakerphone registers register # of bits name comment sctl 1 ens echo suppression unit enable sctl 3 qu echo cancellation unit enable sctl 1 md speakerphone or loudhearing mode sctl 1 agx agcx enable
psb 2170 functional units preliminary data sheet 47 10.99 2.1.4 comfort noise generator the full duplex speakerphone can be extended by a comfort noise generator which can enhance the performance of the speakerphone in noisy environments. the purpose of the comfort noise is to reduce signal modulation when the echo suppression unit switches the attenuation. the operation is as follows: as long as the echo suppression unit is in transmit state no additional noise is added to the outgoing signal. in this state there is already the natural noise transmitted to the line. in addition the comfort noise generator estimates the noise at the microphone input when no speech is detected by either of the three speech detectors (sd, sdx, sdr). once the echo suppression unit switches to receive or idle state the comfort noise generator generates noise similar to the external noise and adds this noise to the outgoing signal. figure 26 shows the integration of the comfort noise generator into the speakerphone. sctl 1 agr agcr enable sctl 1 sdx sdx input tap sctl 1 sdr sdr input tap afectl 4 als als value for loudhearing ssrc1 5 i1 input signal 1 (microphone) ssrc1 5 i2 input signal 2 (microphone) ssrc2 5 i3 input signal 3 (line in) ssrc2 5 i4 input signal 4 (line in) table 14 speakerphone registers
psb 2170 functional units preliminary data sheet 48 10.99 figure 26 comfort noise generator - integration into speakerphone if the new blocks sd and comfort noise are removed the remaining blocks resemble the speakerphone as shown in figures 16 and 20. therefore the comfort noise generator can be considered an optional extension to the speakerphone. the new speech detector sd works as the speech detectors sdx and sdr described in section 2.1.3.1. the parameters of the speech detector are thus the same as shown in table 8. the comfort noise generator adapts itself to the currently present noise at the input signal with respect to the energy level and the spectrum. furthermore it is possible to program a constant noise level which is always present (even if there is no noise at the input signal present). the comfort noise generator is enabled with the bit cn in the control register sctl. note that in order to use the comfort noise generator, the noise controlled adaption must be enabled as well. the noise controlled adaptation is described in the next section. there are three parameters for comfort noise generator: 1. the adaptation speed lp 2. the constant noise level const which determines a noise level that is always added. 3. the factor fac by which the present noise is scaled for the output of the noise generator. table 15 shows the associated registers. control fir nlms wf ghx lgax agcx scas sdx agcr scls lgar sdr ghr control - comfort noise sd nr
psb 2170 functional units preliminary data sheet 49 10.99 as described in chapter 3.7 in detail, several modules must be disabled before the comfort noise generator is enabled. also some parameters of the disabled modules are overwritten by the noise controlled adaptation. this means that if these disabled modules are going to be enabled after the comfort noise generator has been used, these parameters must be set again. 2.1.5 noise controlled adaptation several quantities that are important for the full-duplex speakerphone depend on the level of the background noise. an easy example is the correlation between the signal at the microphone and the signal at the loudspeaker in case of single talk from the line side. obviously, if no noise is present at the near end side, the signal at the microphone is only generated by the acoustic echo of the signal from the loudspeaker and thus very similar to the signal from the loudspeaker. in case of noise at the near end side, the similarity of the signals is minor. since such quantities as this correlation depend on the noise level at the near end side, some parameters must depend on the noise level in order to ensure true full-duplex speakerphone quality. this is meant with the term ? noise controlled adaption ? . the noise controlled adaptation is enabled by setting the bit nad in the control register sctl. the adjustments described in the sequel depend on the level of the noise at the near end side. the noise level is determined as follows. in case the speech detector sd, which is described in section 2.1.4, indicates that no speech is present, then the energy of the microphone signal filtered by a low pass is called the noise level l . in case the speech detector sd indicates speech, then the last output of the low pass is called noise level l . the time constant of the low pass is programmable with the parameter tc as shown in table 16. table 15 comfort noise generator registers register # of bits name comment sctl 1 cn comfort noise enable (bit nad must be set) sccn1 15 const level of constant noise sccn2 15 fac factor for multiplication sccn3 15 lp adaptation time constant
psb 2170 functional units preliminary data sheet 50 10.99 table 16 general noise control adaption register register # of bits name comment sctl 1 nad noise adaptation enable sclpt 15 tc time constant for the low pass
psb 2170 functional units preliminary data sheet 51 10.99 2.1.5.1 correlation adaptation the control block (figures 14 and 16) of the echo cancellation unit monitors the correlation between the loudspeaker signal and the microphone signal. only when the correlation of the loudspeaker and microphone signal exceeds a threshold t , the attenuation achieved by the echo cancellation unit is measured. in a noisy environment the correlation will decrease even if the echo cancellation unit is fully adapted. therefore the threshold t might not be exceeded in this situation. as a result the echo cancellation unit would not report any achieved echo return loss enhancement and thus the echo suppression unit would have to provide all of the desired attenuation. to avoid this situation the threshold t can be adjusted dynamically with the noise level l . figure 27 shows the available parameters for the adaptation of the threshold. figure 27 correlation adaptation as long as the noise level l is less than the threshold nth the threshold t remains at its programmed value corr. this parameter has only an effect when the noise controlled adaption is enabled (sctl:nad is set). if the noise controlled adaption is disabled, a default value is used instead. with enabled noise controlled adaption, once the threshold nth is exceeded, the correlation threshold decreases with the programmable slope cs. however, the threshold will not fall below the programmable limit limit even if the noise level l increases further. table 17 shows the registers associated with the correlation adaptation. table 17 correlation adaptation registers register # of bits name comment sccr 14 corr factor c sccrn 15 nth noise threshold sccrs 12 cs slope sccrl 14 limit limit for c l t limit nth cs corr
psb 2170 functional units preliminary data sheet 52 10.99 2.1.5.2 double talk detection adaptation during double talk the necessary echo return loss for comfortable full duplex conversation may be reduced. the provides the parameter saedtr:aecdtr for this purpose. double talk is detected when the difference between the signal before and after the echo cancellation (subtraction point) suddenly decreases by an amount d . the noisier the environment gets the smaller the amount d should be. otherwise the echo cancellation would fail to detect the relatively smaller change that indicates a double talk detection. figure 28 shows the provisions made by the for an adaptive double talk detection. figure 28 double talk detection adaptation as long as the noise level l is less than the threshold nth the necessary difference d remains at its programmed value aecdtm. once the threshold is exceeded, d decreases with the programmable slope dts. however, it will not fall below the programmable limit limit even if the noise level l increases further. table 18 shows the registers associated with the double talk detection adaptation. table 18 double talk detection adaptation registers register # of bits name comment saedtl 15 aecdtm minimum energy to detect double talk. scdtn 15 nth noise threshold scdts 12 dts slope scdtl 15 limit limit for dtd l d limit nth dts aecdtm
psb 2170 functional units preliminary data sheet 53 10.99 2.1.5.3 adaptive attenuation reduction in noisy environments it is acceptable to reduce the total attenuation att (chapter 2.1) as the noise level increases. this is due to the fact that the noise already presents some kind of local talk. hence an increased echo is not perceived as disturbing as in a silent environment. in order to exploit this, the provides an attenuation decrease dependent on the noise level: att = a sofar - atr, where a sofar is the attenuation provided by the echo cancellation and echo suppression as described in chapters 2.1.1 to 2.1.3. figure 29 shows the attenuation reduction provided by the . figure 29 adaptive attenuation reduction as long as the noise level l is less than the threshold nth the total attenuation is not reduced at all. once the threshold exceeded, the total attenuation is decreased more and more by increasing atr. the sensitivity is programmable by the parameter as. however, atr will not exceed the programmable limit limit even if the noise level l increases further. table 19 shows the registers associated with the adaptive attenuation reduction. the adaptive attenuation reduction influences the attenuation provided by ghx and ghr. thus if the attenuation of the stages is set to 0 db, the adaptive attenuation reduction has no influence as the attenuation of ghx or ghr can never drop below 0 db. table 19 adaptive attenuation reduction registers register # of bits name comment scattn 15 nth noise threshold scatts 15 as attenuation sensitivity scattl 15 limit limit for dtd l atr limit nth as
psb 2170 functional units preliminary data sheet 54 10.99 2.1.5.4 loudspeaker gain adaptation in noisy environments it is useful to automatically increase the signal level of the loudspeaker output with increasing noise level. the features such an automatic gain adaptation by adding additional gain to the module lgar described in section 2.1.3.7. figure 30 illustrates the additional gain provided by the . figure 30 loudspeaker gain adaptation as long as the noise level l is less than the threshold nth there is no additional gain. once the threshold is exceeded, the gain g is increased with the programmable sensitivity gs. however, it will not exceed the programmable limit limit even if the noise level l increases further. table 20 shows the registers associated with the loudspeaker gain adaptation. note: the total attenuation programmed for the speakerphone in register satt1:att is not automatically increased when the loudspeaker gain adaptation increases. therefore, the adaptive attenuation reduction (chapter 2.1.5.3) should be reduced accordingly. table 20 loudspeaker gain adaptation registers register # of bits name comment sclspn 15 nth noise threshold sclsps 15 gs gain sensitivity sclspl 15 limit limit for g l g limit nth gs
psb 2170 functional units preliminary data sheet 55 10.99 2.2 line echo cancellation unit the contains an adaptive line echo cancellation unit for the cancellation of near end echoes. the unit has three modes: the two modes normal mode and superior mode consider up to 4 ms echo length. in superior mode, a shadow filter is used additionally to the normal mode in order to improve the echo cancellation quality. the third mode is the extended mode. it works basically like the superior mode but considers line echoes of up to 8 ms echo length. the line echo cancellation unit is especially useful in front of the various detectors (dtmf, cpt, etc.). a block diagram is shown in figure 31. figure 31 line echo cancellation unit - block diagram input i 2 is usually connected to the line input while input i 1 is connected to the outgoing signal. in normal mode the adaptation process is controlled by the three parameters min, att and mgn. adaptation takes place only if both of the following conditions hold: 1. 2. with the first condition, adaptation to weak signals can be avoided. the second condition avoids adaptation during double talk. the parameter att represents the echo loss provided by external circuitry. the adaptation stops if the power of the received signal (i2) exceeds the power of the expected signal (i1-att) by more than the margin mgn. + - adaptive filter i 2 s 15 i 1 i1 min > i1 att mgn + ? i2 > 1 functional units
psb 2170 functional units preliminary data sheet 56 10.99 figure 32 line echo cancellation unit - superior mode with shadow fir the basic idea of the superior mode is shown in figure 32. the shadow fir filter on the left hand side gets its coefficients adapted similarly to the adaptive filter of the line echo canceller in normal mode. for cancelling the line echo, however, the fir filter on the right hand side is used. when the quality of this fir filter is excelled by the quality of the shadow fir filter, the coefficients of the shadow fir filter are copied to the fir on the right hand side. more formally, the coefficients of the shadow fir filter are adapted (see unit ? adapt coeff ? in figure 32) if similar to normal mode, the following two conditions hold: 1. 2. in this case, att is already the difference between external echo loss and margin (att superior = att normal - mgn normal ) so that the condition is actually the same as for normal mode. the parameter att should be adjusted accordingly. note that att can now be negative. the coefficients are copied from the shadow fir filter to the actually used fir filter (see unit ? copy coeff. ? in figure 32) if 1. currently the adaptation of the shadow fir filter is in progress and at least one of the following two conditions holds:. 2. the attenuation of the shadow fir filter atts is better than the attenuation of the actually used fir filter atta by a margin mgn. note that in superior mode, the parameter mgn has a different meaning than in normal mode 3. the current attenuation atts of the shadow fir is better than at any time since the last update according to condition 2. + - filter fir i 2 s 15 i 1 fir shadow filter adapt copy coeff. coeff. i1 min > i1 i2 ? att ? 0 > atts atta ? mgn > tts t () max atts t 1 ? () atts last time condition 2 has been valid () ,, () >
psb 2170 functional units preliminary data sheet 57 10.99 the extended mode works like the superior mode but the fir considers line echoes of up to 8 ms echo length. since the computational effort increases with increasing fir length, the parameter sp offers a trade-off between adaptation speed and computational costs. with sp set, all shadow fir parameters are adapted every 125 us and thus the adaptation speed is as in superior mode. with sp cleared, half the shadow fir parameters are updated every 125 us in such a way that one half of the parameters and the other half are updated alternately. as indicated in table 50, the computational costs decrease and so does the adaptation speed of the line echo canceller. table 21 shows the registers associated with the line echo canceller. the adaptation of the coefficients can be stopped by setting bit as in register lecctl. this holds for all three modes of the line echo canceller. furthermore for superior and extended mode, also copying the coefficients from the shadow fir is disabled. 2.3 dtmf detector the contains an dtmf detector that recognizes the sixteen standard dtmf tones. figure 33 shows a block diagram of the dtmf detector. the results of the detector are available in the status and a dedicated result register. these registers can be read by the external controller via the serial control interface (sci). table 21 line echo cancellation unit registers register # of bits name comment relevant mode lecctl 1 en line echo canceller enable all lecctl 2 cm 00: normal mode 01: superior mode 10: extended mode 11: reserved all lecctl 1 as adaptation stop all lecctl 1 sp adaptation speed extended lecctl 5 i2 input signal selection for i 2 all lecctl 5 i1 input signal selection for i 1 all leclev 15 min minimal power for signal i 1 all lecatt 15 att externally provided attenuation (i 1 to i 2 )all lecmgn 15 mgn margin all
psb 2170 functional units preliminary data sheet 58 10.99 figure 33 dtmf detector - block diagram table 22 to 24 show the associated registers. as soon as a valid dtmf tone is recognized, the status word and the dtmf tone code are updated (table 23). dtv is set when a dtmf tone is currently recognized and cleared when no dtmf tone is recognized or the detector is disabled. the code for the dtmf tone is provided in register ddctl. dtc is valid when dtv is set and until the next incoming dtmf tone. the registers ddtw and ddlev contain the parameters for detection (table 24). 2.4 call progress tone detector the selected signal is monitored continuously for a call progress tone. the cpt detector consists of a band-pass and an optional timing checker (figure 34). table 22 dtmf detector control register register # of bits name comment ddctl 1 en dtmf detector enable ddctl 5 i1 input signal selection table 23 dtmf detector results register # of bits name comment status 1 dtv dtmf code valid ddctl 5 dtc dtmf tone code table 24 dtmf detector parameters register # of bits name comment ddtw 15 twist twist for dtmf recognition ddlev 6 min minimum signal level to detect dtmf tones dtmf sci i 1 detector
psb 2170 functional units preliminary data sheet 59 10.99 figure 34 call progress tone detector - block diagram the cpt detector can be used in two modes: raw and cooked. in raw mode, the occurrence of a signal within the frequency, time and energy limits is directly reported. the timing checker is bypassed and therefore the does not interpret the length or any interval of the signal. in cooked mode, the number and duration of signal bursts are interpreted by the timing checker. a signal burst followed by a gap is called a cycle. cooked mode requires a minimum of two cycles. the cpt flag is set with the first burst after the programmed number of cycles has been detected. the cpt flag remains set until the unit is disabled or speech is detected, even if the conditions are not met anymore. in this mode the cpt is modelled as a sequence of identical bursts separated by gaps with identical length. the can be programmed to accept a range for both the burst and the gap. it is also possible to specify a maximum aberration of two consecutive bursts and gaps. figure 35 shows the parameters for a single cycle (burst and gap). figure 35 call progress tone detector- cooked mode the status bit is defined as follows: timing band-pass sci (status) i 1 300-640 hz checker t pmax t pmin t gmin t gmax
psb 2170 functional units preliminary data sheet 60 10.99 cpt is not affected by reading the status word. it is automatically reset when the unit is disabled. table 26 shows the control register for the cpt detector. if any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst. note: in cooked mode cpt is set with the first burst after the programmed number of cycles has been detected. if cpttr:num = 2, then cpt is set with the third signal burst. note: the number of cycles must be set to zero in raw mode. 2.5 alert tone detector the alert tone detector can detect the standard alert tones (2130 hz and 2750 hz) for caller id protocols. the results of the detector are available in the status register and register atdctl0. these registers can be read by the external controller via the serial control interface (sci). table 25 call progress tone detector results register # of bits name comment status 1 cpt cp tone currently detected [340 hz; 640 hz] table 26 call progress tone detector registers register # of bits name comment cptctl 1 en unit enable cptctl 1 md mode (cooked, raw) cptctl 5 i1 input signal selection cptmn 8 minb minimum time of a signal burst (t pmin ) cptmn 8 ming minimum time of a signal gap (t gmin ) cptmx 8 maxb maximum time of a signal burst (t pmax ) cptmx 8 maxg maximum time of a signal gap (t gmax ) cptdt 8 difb maximum difference between consecutive bursts cptdt 8 difg maximum difference between consecutive gaps cpttr 3 num number of cycles (cooked mode), 0 (raw mode) cpttr 8 min minimum signal level to detect tones cpttr 4 sn minimal signal-to-noise ratio
psb 2170 functional units preliminary data sheet 61 10.99 figure 36 alert tone detector - block diagram as soon as a valid alert tone is recognized, the status word of the and the code for the detected combination of alert tones are updated (table 28). with on hook mode selected, the end of the alert tone can be detected faster. on hook mode assumes that there is no speech signal present. 2.5.1 universal tone detector the universal tone detector can be used instead of the cpt detector to detect special tones which are not covered by the standard cpt band-pass. figure 37 shows the functional block diagram. table 27 alert tone detector registers register # of bits name comment atdctl0 1 en alert tone detector enable atdctl0 5 i1 input signal selection atdctl1 1 md detection of dual tones or single tones atdctl1 1 onh on hook mode atdctl1 1 dev maximum deviation (0.5% or 1.1%) atdctl1 8 min minimum signal level to detect alert tones table 28 alert tone detector results register # of bits name comment status 1 atv alert tone detected atdctl0 2 atc alert tone code alert tone sci i 1 detector
psb 2170 functional units preliminary data sheet 62 10.99 a figure 37 universal tone detector - block diagram initially, the input signal is filtered by a programmable band-pass (center frequency cf and band width bw ). both the in-band signal (upper path) and the out-of-band signal are determined (lower path) and the absolute value is calculated. both signals are furthermore filtered by a limiter and a low-pass. all signal samples (absolute values) below a programmable limit lim are set to zero and all other signal samples are diminished by lim . the purpose of the limiter is to increase noise robustness. after the limiter stages both signals are filtered by a fixed low pass. the evaluation logic block determines when to set and when to reset the status bit status:utd. the status bit will be set if both of the following conditions hold for at least time ttone without breaks exceeding time tb1 : 1. the in-band signal exceeds a programmable level lev 2. the difference of the in-band and the out-of-band signal exceeds delta the status bit will be reset if at least one of these conditions is violated by at least time tgap without breaks exceeding tb2 . the times tb1 and tb2 help to reduce the effects of sporadic dropouts. example: ttone is set to 100 ms and tb1 is set to 4 ms. the conditions are met for 30ms, then violated for 3ms and then met again for 80 ms. in this case the break of 3ms is ignored, because it does not exceed the allowed break time tb1. therefore the status bit will be set after 100 ms. table 29 summarizes the associated registers. i 1 evaluation logic sci programmable band-pass lp lp limit limit |x| |x|
psb 2170 functional units preliminary data sheet 63 10.99 the result is available in the status register (table30). note: the utd bit is at the same position as the cpt bit. therefore the cpt detector and the programmable band-pass must not run at the same time. 2.6 caller id decoder the caller id decoder is basically a 1200 baud modem (fsk, demodulation only). the bit stream is formatted by a subsequent uart and the data is available in a data register along with status information (figure 38). figure 38 caller id decoder - block diagram table 29 universal tone detector registers register # of bits name comment utdctl 1 en utd detector enable utdctl 5 i1 input signal selection utdbw 15 bw bandwidth of band-pass utdcf 15 cf center frequency of band-pass utdlim 15 lim limiter level utdlev 15 lev minimum signal level (in-band) utddlt 15 delta minimum difference (in-band, out-of-band) utdtmt 8 ttone minimum time to set status bit utdtmt 8 tb1 maximum break time for ttone utdtmg 8 tgap minimum time to reset status bit utdtmg 8 tb2 maximum break time for tgap table 30 universal tone detector results register # of bits name comment status 1 utd tone detected uart fsk demod. sci (status, data) i 1 (bellcore, v.23)
psb 2170 functional units preliminary data sheet 64 10.99 the fsk demodulator supports two modes according to table 31. the appropriate mode is detected automatically. the cid decoder does not interpret the data received. each byte received is placed into the cidctl register (table 33). the status byte of the is updated (table 32). cia and cd are cleared when the unit is disabled. in addition, cia is cleared when cidctl0 is read. when the cid unit is enabled, it waits for a programmable number of continuous mark bits (cidctl1:nmb). these mark bits may optionally be preceded by a channel seizure signal consisting of a series of alternating space and mark signals. if such a channel table 31 caller id decoder modes mode mark (hz) space (hz) comment 1 1200 2200 bellcore 2 1300 2100 v.23 table 32 caller id decoder status register # of bits name comment status 1 cia cid byte received status 1 cd carrier detected table 33 caller id decoder registers register # of bits name comment cidctl0 1 en unit enable cidctl0 1 dot drop out tolerance during mark or seizure sequence cidctl0 1 cm compatibility mode cidctl0 5 i1 input signal selection cidctl0 8 data last cid data byte received cidctl1 5 nmss number of mark/space sequences necessary for successful detection of carrier. cidctl1 5 nmb number of mark bits necessary before space of first byte after carrier detected. cidctl1 6 min minimum signal level for cid detection.
psb 2170 functional units preliminary data sheet 65 10.99 seizure sequence is present it must consist of at least cidctl1:nmss alternating mark and space bits. once the programmed number of continuous mark bits has been received the sets the carrier detect bit status:cd. the interpretation of the data, including message type, length and checksum is completely left to the controller. the cid unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself. there are two alternative caller id decoders. with bit cm cleared, the standard caller id decoder is selected, which is compatible to psb 2170 version 1.1. the standard called id decoder requires a seizure sequence. with cm set to 1, the improved caller id decoder is selected, which provides a higher twist tolerance, does not require a seizure sequence, and allows to select the drop out tolerance. the drop out tolerance is selected by bit dot of register cidctl0. then, drop outs during a mark sequence do not necessarily cause that the cid detection looses its carrier sequence, but the received mark sequence can be recognized although there are drop outs. the same holds for a seizure sequence. this behavior meets the bellcore test specification. if drop out tolerance is enabled, the six registers cidmf1 to cidmf6 have to be programmed prior to use of this feature. note that these registers are undefined after reset. the registers cidmf1 to cidmf6 must contain all possible message formats, which can be transmitted after the mark sequence, and these registers must not contain any other value. for bellcore for example, the valid message formats are 04 h , 06 h , 80 h and 82 h so that registers cidmf1 to cidmf6 may contain 04 h , 06 h , 80 h , 82 h , 82 h and 82 h . note: some caller id mechanism may require additional external components for dc decoupling. these tasks must be handled by the controller. note: the controller is responsible for selecting and storing parts of the cid as needed. 2.7 dtmf generator the dtmf generator can generate single or dual tones with programmable frequency and gain. this unit is primarily used to generate the common dtmf tones but can also be used for signalling or other user defined tones. a block diagram is shown in figure 39.
psb 2170 functional units preliminary data sheet 66 10.99 figure 39 dtmf generator - block diagram both generators and amplifiers are identical. there are two modes for programming the generators, cooked mode and raw mode. in cooked mode, dtmf tones are generated by programming a single 4 bit code. in raw mode, the frequency of each generator/ amplifier can be programmed individually by a separate register. the unit has two outputs which provide the same signal but with individually programmable attenuation. table 34 shows the parameters of this unit. note: dgf1 and dgf2 are undefined when cooked mode is used and must not be written. 2.8 analog interface there are two identical interfaces to the analog side (i.e., the analog fronend described in chapter 4.3) as shown in figure 40. these interfaces must be connected to a double codec like the psb 4851. table 34 dtmf generator registers register # of bits name comment dgctl 1 en enable for generators dgctl 1 md mode (cooked/raw) dgctl 4 dtc dtmf code (cooked mode) dgf1 15 frq1 frequency of generator 1 dgf2 15 frq2 frequency of generator 2 dgl 7 lev1 level of amplifier for generator 1 dgl 7 lev2 level of amplifier for generator 2 dgatt 8 att1 attenuation of s 9 dgatt 8 att2 attenuation of s 10 f 1 f 2 generator generator ampl1 ampl2 att2 s 9 s 10 att1
psb 2170 functional units preliminary data sheet 67 10.99 figure 40 analog frontend interface - block diagram for each signal an amplifier is provided for level adjustment. the ingoing signals can be passed through an optional high-pass (hp) to get rid of any dc part. furthermore, up to three signals can be mixed in order to generate the outgoing signals (s 2 ,s 4 ). table 35 shows the associated registers. 2.9 digital interface there are two almost identical interfaces to the digital side (i.e., the ssdi/iom ? -2 interface described in chapters 4.1 and 4.2) as shown in figure 41. the only difference between these two interfaces is that only channel 1 supports the ssdi mode. table 35 analog frontend interface registers register # of bits name comment ifg1 16 ig1 gain for ig1 ifg2 16 ig2 gain for ig2 ifs1 1 hp high-pass for s 1 ifs1 5 i1 input signal 1 for ig2 ifs1 5 i2 input signal 2 for ig2 ifs1 5 i3 input signal 3 for ig2 ifg3 16 ig3 gain for ig3 ifg4 16 ig4 gain for ig4 ifs2 1 hp high-pass for s 3 ifs2 5 i1 input signal 1 for ig4 ifs2 5 i2 input signal 2 for ig4 ifs2 5 i3 input signal 3 for ig4 channel 2 s 1 channel 1 s 2 i 1 i 2 i 3 line out line in ig1 ig2 s 3 s 4 i 1 i 2 i 3 loudspeaker microphone ig4 hp ig3 hp
psb 2170 functional units preliminary data sheet 68 10.99 figure 41 digital interface - block diagram each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (att). the attenuator can be used for artificial echo loss. each input can be passed through an optional high-pass (hp) to get rid of any dc part. channel 2 of the iom ? -2 can be split into two consecutive 8 bit channels with independent data streams (a-law or - law). it is therefore possible to use either two 16 bit linear channels, a 16 bit channel and an 8 bit channel, a 16 bit channel and two 8 bit channels or three 8 bit channels. the associated registers are shown in table 36. table 36 digital interface registers register # of bits name comment ifs3 5 i1 input signal 1 for s 6 ifs3 5 i2 input signal 2 for s 6 ifs3 5 i3 input signal 3 for s 6 ifs3 1 hp high-pass for s 5 ifs4 5 i1 input signal 1 for s 8 ifs4 5 i2 input signal 2 for s 8 ifs4 5 i3 input signal 3 for s 8 ifs4 1 hp high-pass for s 7 ifs4 5 i1 input signal 1 for s 24 ifs4 5 i2 input signal 2 for s 24 channel 2/3 (iom ? -2 interface) channel 1 (ssdi/iom ? -2 interface) s 7 /s 23 s 8 /s 24 i 1 i 2 i 3 att2/3 hp s 5 s 6 i 1 i 2 i 3 att1 hp
psb 2170 functional units preliminary data sheet 69 10.99 2.10 universal attenuator the contains an universal attenuator that can be connected to any signal (e.g. for sidetone gain in isdn applications). figure 42 universal attenuator - block diagram table 37 shows the associated register. 2.11 automatic gain control unit in addition to the universal attenuator with programmable but fixed gain the contains an amplifier with automatic gain control (agc). the agc is preceded by a signal summation point for two input signals. one of the input signals can be attenuated. ifs4 5 i3 input signal 3 for s 24 ifs4 1 hp high-pass for s 23 ifg5 8 att1 attenuation for input signal i3 (channel 1) ifg5 8 att2 attenuation for input signal i3 (channel 2) ifg5 8 att3 attenuation for input signal i3 (channel 3) table 37 universal attenuator registers register # of bits name comment ua 8 att attenuation for ua ua 5 i1 input signal for ua table 36 digital interface registers register # of bits name comment s 14 ua i 1
psb 2170 functional units preliminary data sheet 70 10.99 figure 43 automatic gain control unit - block diagram the operation of the agc is similar to agcx (accr) of the speakerphone. the differences are as follows: no nois parameter separate enable/disable control slightly different coefficient format furthermore the agc contains a comparator that starts and stops the gain regulation. the signal after the summation point (s17) is filtered by a peak detector with time constant dec for decay. then the signal is compared to a programmable limit lim. regulation takes only place when the filtered signal exceeds the limit. table 38 shows the associated registers. table 38 automatic gain control registers register # of bits name comment agcctl 1 en enable agcctl 5 i1 input signal 1 for agc agcctl 5 i2 input signal 2 for agc agcatt 15 att attenuation for i 2 agc1 8 ag_init initial agc gain/attenuation agc1 8 com compare level rel. to max. pcm-value agc2 8 speedl change rate for lower levels agc2 8 speedh change rate for higher level agc3 7 ag_att attenuation range agc3 8 ag_gain gain range agc4 7 dec time constant for decay rate of peak detector agc4 8 lim comparator minimal signal level agc5 7 lp agc low pass time constant s 16 agc i 1 att i 2 s 17
psb 2170 functional units preliminary data sheet 71 10.99 2.12 noise reduction unit additionally to the noise reduction block built in the speakerphone, another noise reduction block is available as configurable module. it can be useful for reducing the noise coming in the receive path from the line side. figure 44 noise reduction - block diagram the noise reduction unit attenuates frequencies with a great ratio of the noise energy level to the level of the speach signal. the maximal attenuation of the noise reduction unit can be programmed by the parameter nratt. there are some restrictions for the simultaneous selection of the speakerphone. different trade-offs can be selected with the parameter md. 2.13 equalizer the contains two identical equalizers which can be programmed individually. each equalizer can be inserted into any signal path. the main application for the equalizer is the correction of the frequency characteristics of the microphone, transducer or loudspeaker. each equalizer consists of an iir filter followed by an fir filter as shown in figure 45. table 39 noise reduction registers register # of bits name comment nrctl 1 en noise reduction unit enable nrctl 2 md select restriction of speakerphone nrctl 5 i1 input signal selection nratt 15 nratt maximal attenuation of the noise reduction unit. noise s 25 i 1 reduction
psb 2170 functional units preliminary data sheet 72 10.99 figure 45 equalizer - block diagram the coefficients a 1 -a 9 , b 2 -b 9 and c 1 belong to the iir filter, the coefficients d 1- d 17 and c 2 belong to the fir filter. table 40 shows the registers associated with the first equalizer (s 18 ). the second equalizer (s 19 ) is programmed by the registers fcfctl2 and fcfcof2, respectively due to the multitude of coefficients the psb 2170 uses an indirect addressing scheme for reading or writing an individual coefficient. the address of the coefficient is given by adr and the actual value is read or written to register fcfcof1. table 40 equalizer registers register # of bits name comment fcfctl1 1 en enable fcfctl1 5 i input signal for equalizer fcfctl1 6 adr filter coefficient address fcfcof1 16 v filter coefficient data z -1 z -1 z -1 a1 a2 a9 z -1 z -1 z -1 c1 b2 b9 z -1 z -1 z -1 d1 d2 d17 c2 s 18 /s 19 i fir iir
psb 2170 functional units preliminary data sheet 73 10.99 in order to ease programming the automatically increments the address adr after each access to fcfcof1. note: any access to an out-of-range address automatically resets fcfctl1:adr. 2.14 tone generator the contains a universal tone generator which can be used for tone alerting, call progress tones or other audible feedback tones. figure 46 shows a block diagram of this unit. figure 46 tone generator - block diagram the heart of this unit are the four independent sine/square wave generators that can generate individually programmable frequencies (f 1 , f 2 , f 3 , f 4 ). each generator has an associated amplifier (g 1 , g 2 , g 3 , g 4 ). the dynamic behavior of the tone generator is controlled by the beat generator. if the beat generator is enabled, then the output is either a three tone cadence or a two tone caddence as shown in figure 47. control generator t on , t off beat generator automatic stop t 1 , t 2 , t 3 sine/square wave generators f 1 , f 2 , f 3, f 4 gain g 1 , g 2 , g 3, g 4 go 1 go 2 s 20 s 21
psb 2170 functional units preliminary data sheet 74 10.99 figure 47 tone generator - tone sequences the duration of each frequency is defined by t 1 , t 2 and t 3 . for each timeslot either the associated frequency can be generated or a frequency pair (table 41). if the beat generator is disabled, then the output is a continuous signal of either f 1 , f 2 , f 1 +f 4 , f 2 +f 4 or silence. the control generator is used to enable the beat generator (during t on ) and disable it during t off . with the automatic stop feature, the cadence generation of the beat generator stops not immediately but after the end of a cadence (either t 2 or t 3 ). this avoids unpleasant sounds when stopping the tone generator unit. table 42 shows the registers associated with the tone and ringing generator. table 41 tone generator modes timeslot option 1 option 2 t 1 f 1 f 1 +f 4 t 2 f 2 f 2 +f 4 t 3 f 3 f 3 +f 4 table 42 tone generator registers register # of bits name comment status 1 tg status bit (tone generator on/off) tgctl 2 cgm control generator mode tgctl 1 dt dual tone enable (f4 on/off) tgctl 2 bgm beat generator mode (f1, f2, f1/f2 or f1/f2/f3) tgctl 1 sm stop mode (immediate or automatic) tgctl 1 wf waveform (sine or square) t 1 t 2 f 1 f 2 t 1 t 2 t 3 f 1 f 2 f 3 t 1 t 2 t 3 f 1 f 2 f 3 t 1 t 2 f 1 f 2 t 1 t 2 f 1 f 2 f f tt three tone cadence two tone cadence
psb 2170 functional units preliminary data sheet 75 10.99 this unit has two outputs (s 20 and s 21 ). the signal level of these outputs can be programmed individually by the preceding gain stages (go 1 and go 2 ). 2.15 peak detector the peak detector (figure 48) provides an easy means to verify the minimum or maximum signal level of any signal s i within the . it is, however, usually not used in normal operation. the peak detector stores either the maximum or the minimum signal value of the observed signal i 1 in the register pddata since the last read access to this register. therefore it is not only possible to determine the absolute level of the signal but it can also be checked whether a dc offset is present. this can be done by first scanning for the maximum and then for the minimum value. if the minimum value is not (approximately) the negated maximum value then a dc offset is present. the peak detector should be disabled if not needed. tgton 16 t on tgtoff 16 t off tgt1 16 t 1 tgt2 16 t 2 tgt3 16 t 3 tgf1 15 f 1 tgf2 15 f 2 tgf3 15 f 3 tgf4 15 f 4 tgg1 15 g 1 tgg2 15 g 2 tgg3 15 g 3 tgg4 15 g 4 tggo1 15 go 1 tggo2 15 go 2 table 42 tone generator registers register # of bits name comment
psb 2170 functional units preliminary data sheet 76 10.99 figure 48 peak detector - block diagram the register pddata gives the maximum or minimum integer depending on the mode selected by bit mm. as an example it may be assumed that the detection of the maximum is selected. then with enabling the detector and with each read access to register pddata, pddata is set to the smallest possible value, which is the negative maximum integer. with each new maximum detected on signal i1, this maximum is provided by pddata. table 43 peak detector registers register # of bits name comment pdctl 1 en peak detector enable pdctl 1 mm minimum/maximum selection pdctl 5 i1 input signal selection pddata 16 min/max signal value since last read access peak sci i 1 detector
psb 2170 miscellaneous preliminary data sheet 77 10.99 3 miscellaneous miscellaneous miscellaneous 3.1 reset and power down mode the psb 2170 can be in either reset mode, power down mode or active mode. during reset the psb 2170 clears the hardware configuration registers and stops both internal and external activity. with the first access to a read/write register the psb 2170 enters active mode. in this mode the main oscillator is running and normal operation takes place. the psb 2170 can be brought to power down mode by setting the power down bit (pd). in power down mode the main oscillator is sto pped. the psb 2170 enters active mode again upon an access to a read/write register. figure 49 shows a state chart of the modes of the psb 2170. figure 49 operation modes - state chart 3.2 sps control register the two sps outputs (sps 0 , sps 1 ) can be used either as general purpose outputs , speakerphone status outputs or as status register outputs. this is programmed with the bits mode. table 45 shows the associated register. table 44 power down bit register # of bits name comment cctl 1 pd power down mode reset active mode power down mode mode cctrl.pd=1 r/w reg. access rst=1 rst=1 r/w reg. access
psb 2170 miscellaneous preliminary data sheet 78 10.99 when used as status register outputs, the status register bit at position pos appears at sps 0 and the bit at position pos+1 appears at sps 1 . this mode of operation can be used for debugging purposes or direct polling of status register bits. the rdy bit cannot be observed via sp0 or sp1. 3.3 interrupt the can generate an interrupt to inform the host of an update of the status register according to table 46. an interrupt mask register (intm) can be used to disable or enable the interrupting capability of each bit of the status register individually. table 45 sps register spsctl 1 sp0 output value of sps 0 spsctl 1 sp1 output value of sps 1 spsctl 3 mode mode of operation spsctl 4 pos position for status register window table 46 interrupt source summary status (old) status (new) set by reset by rdy=0 rdy=1 command completed command issued cia=0 cia=1 new caller id byte available cidctl0 read or en=0 1) 1) en=0 denotes unit disable cd=0 cd=1 carrier detected carrier lost or en=0 cd=1 cd=0 carrier lost or en=0 carrier detected tg=1 tg=0 tone generator active tone sequence finished or en=0 dtv=0 dtv=1 dtmf tone detected dtmf tone lost or en=0 dtv=1 dtv=0 dtmf tone lost or en=0 dtmf tone detected atv=0 atv=1 alert tone detected alert tone lost or en=0 atv=1 atv=0 alert tone lost or en=0 alert tone detected cpt/utd=0 cpt/utd=1 cpt or ut detected cpt or ut lost cpt/utd=1 cpt/utd=0 cpt or ut lost cpt or ut detected ppi=0 ppi=1 event at app input pin detected register dhold read abt=0 abt=1 exception (non-maskable) write to rev register
psb 2170 miscellaneous preliminary data sheet 79 10.99 an interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. the interrupts are issued immedeately after the status register update. the status register update for the event set bit cia, cd, dtv, atv, apt, utd, ppi or abt is performed immediately after the event occurs that causes the bit to be set. for the event clear bit cd, dtv, atv, cpt or utd, the status register update is performed with the next update of the rdy bit, i.e., up to 125 us after the event occurs that causes the bit to be set. for the event clear bit tg, the status register update is performed 125 us after the update of the rdy bit as the latest. this internal interrupt is cleared only when the host executes the data read access with interrupt acknowledge command. in this case, the internal interrupt is cleared when the first bit of the status register is output. if a new event occurs while the host reads the status register, the status register is updated after the current access is terminated and a new interrupt is internally generated immediately after the access has ended. 3.4 abort if the detects a corrupted configuration (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. the discards all commands with the exception of a write command to the revision register while abt is set. only after the write command to the revision register (with any value) the abt bit is reset and a reinitialization can take place. 3.5 revision register the contains a revision register. this register is read only and does not influence operation in any way. a write to the revision register clears the abt bit of the status register but does not alter the content of the revision register. 3.6 hardware configuration the can be adapted to various external hardware configurations by two special registers: hwconfig0 and hwconfig1. these registers are written once during initialization and must not be changed while the is in active mode. 3.6.1 frame synchronization the locks itself to either an externally supplied frame sync signal or generates the frame sync signal itself. this internal reference frame sync signal is called master frame sync (mfsc). table 47 shows how afeclk and mfsc are derived by the . the bits act and mfs are contained in the hardware configuration registers. the bit mfs controls whether the frame sync is taken from external or generated internally. the bit act enables the clock tracking and is explained in the sequel section.
psb 2170 miscellaneous preliminary data sheet 80 10.99 3.6.2 clock tracking the can adjust afeclk and afefsc dynamically to a slightly varying fsc if afeclk and afefsc are derived from the main oscillator (xtal). this mode r equires that both afefsc and fsc are nominally running at the same frequency (8 khz). it is enabled with the bit act in the hardware configuration registers. this feature is especially useful when the fsc signal is not derived from the same clock source as afeclk (isdn application). 3.6.3 afe clock source the can also derive its afeclk from an externally provided clock clk. this can be enabled with the bit acs in the hardware configuration registers. the external clock clk is expected to run at 13.824 mhz. 3.6.4 afe used for clock and frame sync gereration if the afe is not used but a clock and frame sync is required, the can generate such a clock and frame sync at the afe interface. to use this feature, the afe must be disabled and the hwconf3 register (bits cm1 and cm0) can be used for configuration. 3.7 restrictions and mutual dependencies of modules there are some restrictions concerning the modules that can be enabled at the same time (table 48). a checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. table 47 frame synchronization selection act mfs afeclk mfsc application 0 0 xtal afefsc analog featurephone 0 1 - fsc isdn stand-alone 1 1 xtal fsc dect
psb 2170 miscellaneous preliminary data sheet 81 10.99 some incompatible modules share the same internal memory space. if this is for example the case for the incompatible modules a and b, and both modules are going to be used at different times, then the following scenario appears: module a has to be programmed prior to use. after a while, it is disabled, module b is programed and module b is enabled. at a later time, module b is disabled. before module a is enabled, the table 48 dependencies of modules subband (normal) subband (isdn) subband (enhanced) subband (reduced) fullband mode one fullband mode two (< 542 taps) fullband mode two (> = 542 taps) comfort noise noise adaptation dtmf detector caller id (standard) caller id (improved) alert tone detector cpt detector universal tone detector line echo canceller equalizer, dtmf, tone subband (normal) xxxxxxx subband (isdn) x xxxxxxxxxxxxxx subband (enhanced) xx xxxxxxxxxxxxxx subband (reduced) xxx xxx 1) 1) modules can be enabled at the same time. however, deactivation requires proper sequence: first the echo cancellation unit must be disabled, then the dtmf detector. fb one xxxx fb two (< 542 taps) xxxx fb two (>= 542 taps) xxxx x comfort noise xxx x xxxxxxx noise adaptation xx xx xx dtmf detector xx 1) xx caller id (standard) xx xx x caller id (improved) xx xxx x alert tone detector xx x xx cpt detector xx xx x ut detector xx xx x line echo canceller xx x equalizer 1/2, dtmf/tone generator x
psb 2170 miscellaneous preliminary data sheet 82 10.99 parameters of module a must be reprogrammed. this reprograming is necessary for all combination listed in table 49. for the fullband mode two of the echo cancellation unit, a detailed list of the maximal fir length under certain restriction can be found in chapter 2.1.1.1. the freely configurable noise reduction unit (chapter 2.12) has some restrictions not stated in table 48. a detailed description of the restrictions is provided with the register description of register nrctl. a further restriction may occur because of the resource costs of the simultaneously applied modules. each module currently in use takes up some resources. the percentage a module needs from the totally available resources is listed in table 50. the sum of resources all applied modules must never exceed 100. the amounts listed on table 50 are valid for 34.560 mhz operating frequency. if the psb 2170 runs at a higher or lower frequency, the resource costs decrease or increase accordingly. thus, it may be necessary to restrict the length of the fir filter of the echo cancellation unit if several other units are operating at the same time. table 49 reprogram parameters after use of this the parameter of these must be reprogrammed aec fullband mode two which number of taps > 645 dtmf decoder, caller id decoder, alert tone detector, cpt detector, universal tone detector and line echo canceller aec subband mode "isdn" dtmf decoder, caller id decoder, alert tone detector, cpt detector, universal tone detector and line echo canceller aec subband mode "enhanced" dtmf decoder, caller id decoder, alert tone detector, cpt detector, universal tone detector, line echo canceller, equalizers, tone detectors and tone generator comfort noise dtmf decoder, caller id decoder, alert tone detector, cpt detector, universal tone detector and line echo canceller free noise reduction module with nrctl:md=10 dtmf decoder, caller id decoder, alert tone detector, cpt detector, universal tone detector and line echo canceller cpt detector universal tone detector dtmf detector registers cidmf1 to cidmf6 of cid decoder (improved)
psb 2170 miscellaneous preliminary data sheet 83 10.99 table 50 module weights module weight comment cpt detector 5.03 caller id decoder 3.73 / 9.75 cm = 0 / cm = 1 alert tone detector 2.45 / 3.15 off hook / on hook dtmf detector 6.05 ut detector 3.24 dtmf generator 1.92 equalizer 2.50 speakerphone 10.93 agcx 1.92 agcr 1.94 acoustic echo cancellation fullband mode one 32.25 / 41.90 / 51.55 / 61.20 / 70.86 256 taps / 384 taps / 512 taps / 640 taps / 768 taps fir length. acoustic echo cancellation fullband mode two 40.03 / 42.99 / 45.96 / 48.92 / 51.88 256 taps / 384 taps / 512 taps / 640 taps / 768 taps fir length. adaption window: 256 taps acoustic echo cancellation fullband mode two 25.22 fir length: 128 taps. adaption window: 128 taps noise reduction of fb aec 5.03 acoustic echo cancellation subband mode (incl. nr) 32.19 / 33.88 / 35.17 / 37.93 / 39.24 mode: nrn / reduced / normal / isdn / enhanced noise reduction module 7.70 noise controlled adaption 5.07 comfort noise 7.45 line echo cancellation 11.50 / 13.02 normal mode / superior mode 21.60 / 17.04 extended mode, sp = 1/ sp = 0 universal attenuator 0.16 digital interface 1.46 channel 1 or ssdi 1.46 / 3.03 channel 2 / channel 2+3 analog interface 2.11 clock tracking 0.53 miscellaneous 7.70 always active
psb 2170 miscellaneous preliminary data sheet 84 10.99
psb 2170 interfaces preliminary data sheet 85 10.99 4 interfaces interfaces interfaces this section describes the interfaces of the . the supports both an iom ? -2 interface with single and double clock mode and a strobed serial data interface (ssdi). however, these two interfaces cannot be used simultaneously as they share some pins. both interfaces are for data transfer only and cannot be used for programming the . the is slave and the frame synchronization as well as the data clock are inputs. table 51 lists the features of the two alternative interfaces. 4.1 iom ? -2 interface the data stream is partitioned into packets called frames. each frame is divided into a fixed number of timeslots. each timeslot is used to transfer 8 bits. figure 50 shows a commonly used terminal mode (three channels ch 0 , ch 1 and ch 2 with four timeslots each). the first timeslot (in figure 50: b1) is denoted by number 0, the second one (b2) by 1 and so on. figure 50 iom ? -2 interface - frame structure the signal fsc is used to indicate the start of a frame. figure 51 shows as an example two valid fsc-signals (fsc, fsc * ) which both indicate the same clock cycle as the first clock cycle of a new frame (t 1 ). table 51 ssdi vs. iom ? -2 interface iom ? -2 ssdi signals 4 6 channels (bidirectional) 3 1 code linear pcm (16 bit), a-law, -law (8 bit) linear pcm (16 bit) synchronization within frame by timeslot (programmable) by signal (dxst, drst) b1 m0 b2 fsc dd/du ch 0 ch 1 ch 2 125 s ci0 ic1 m1 ic2 ci1 ic4 ic3
psb 2170 interfaces preliminary data sheet 86 10.99 figure 51 ssdi/iom ? -2 interface - frame start the supports both single clock mode and double clock mode. in single clock mode, the bit rate is equal to the clock rate. bits are shifted out with the rising edge of dcl and sampled at the falling edge. in double clock mode, the clock runs at twice the bit rate. therefore for each bit there are two clock cycles. bits are shifted out with the rising edge of the first clock cycle and sampled with the falling edge of the second clock cycle. figure 52 shows the timing for single clock mode and figure 53 shows the timing for double clock mode. figure 52 iom ? -2 interface - single clock mode dcl fsc fsc * t 1 t 2 dcl t 1 t 2 dd/dr du/dx bit 0 bit 1 bit 2 bit 0 bit 1 bit 2
psb 2170 interfaces preliminary data sheet 87 10.99 figure 53 iom ? -2 interface - double clock mode the supports up to three channels simultaneously for data transfer. if only two channels are used, then both the coding (pcm a-law, pcm -law or linear) and the data direction (dd/du assignment for transmit/receive) can be programmed individually. the psb 2170 supports a third channel by simply splitting the second 16 bit channel into two 8 bit channels.therefore the following restrictions occur for channel 2 and 3 in this case: 1. channel two as well as three must use pcm coding (both either a-law or -law) 2. channel three is on an even timeslot 3. channel two is on the following odd timeslot to enabled the channel splitting, bit sdchn2:cs must be set and bit sdchn2:pcm cleared. the selection of bit sdchn2:pcd holds then for both channels. table 52 shows the registers used for configuration of the iom ? -2 interface. table 52 iom ? -2 interface registers register # of bits name comment sdconf 1 en interface enable sdconf 1 dcl selection of clock mode (double/single clock) sdconf 6 nts number of timeslots within frame sdchn1 1 en channel 1 enable sdchn1 6 ts first timeslot (channel 1) sdchn1 1 dd data direction (channel 1) sdchn1 1 pcm 8 bit code or 16 bit linear pcm (channel 1) sdchn1 1 pcd 8 bit code (a-law or -law, channel 1) sdchn2 1 en channel 2 enable sdchn2 1 cs channel 2 split (into two contiguous 8 bit channels) sdchn2 6 ts first timeslot (channel 2) sdchn2 1 dd data direction (channel 2) dcl t 1 dd/dr du/dx bit 0 bit 1 bit 2 bit 0 bit 1 t 2 t 3 t 4 t 5
psb 2170 interfaces preliminary data sheet 88 10.99 in a-law or -law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. in linear mode, 16 bits are needed for a single channel. in this mode, two consecutive timeslots are used for data transfer. bits 8 to 15 are transferred within the first timeslot and bits 0 to 7 are transferred within the next timeslot. the first timeslot must have an even number. figure 54 shows as an example a single channel in linear mode occupying timeslots 2 and 3. each frame consists of six timeslots and single clock mode is used. figure 54 iom ? -2 interface - channel structure at this rate the data is shifted out with the rising edge of the clock and sampled at the falling edge. the data clock runs at 384 khz (six timeslots with 8 bit each within 125 s). sdchn2 1 pcm 8 bit code or 16 bit linear pcm (channel 2) sdchn2 1 pcd 8 bit code (a-law or -law, channel 2) table 52 iom ? -2 interface registers register # of bits name comment fsc dd/du d 15 d 10 d 11 d 12 d 13 d 14 d 9 d 8 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 3
psb 2170 interfaces preliminary data sheet 89 10.99 4.2 ssdi interface the ssdi interface is intended for seamless connection to low-cost burst mode controllers (e.g. pmb 27251) and supports a single channel in each direction. the data stream is partitioned into frames. within each frame one 16 bit value can be sent and received by the psb 2170. the start of a frame is indicated by the rising edge of fsc. data is always latched at the falling edge of dcl and output at the rising edge of dcl. the ssdi transmitter and receiver are operating independently of each other except that both use the same fsc and dcl signal. 4.2.1 ssdi interface - transmitter the psb 2170 indicates outgoing data (on signal dx) by activating dxst for 16 clocks. the signal dxst is activated with the same rising edge of dcl that is used to send the first bit (bit 15) of the data. dxst is deactivated with the first rising edge of dcl after the last bit has been transferred. the psb 2170 drives the signal dx only when dxst is activated. figure 55 shows the timing for the transmitter. figure 55 ssdi interface - transmitter timing 4.2.2 ssdi interface - receiver valid data is indicated by an active drst pulse. each drst pulse must last for exactly 16 dcl clocks. as there may be more than one drst puls within a single frame the psb 2170 can be programmed with the parameter nas to listen to the n-th pulse with n ranging from 1 to 16. in order to detect the first pulse properly, drst must not be active at the rising edge of fsc. in figure 57 the psb 2170 is listening to the third drst pulse (n=3). fsc 125 s dxst dcl du/dx bit 15 bit 14 bit 1 bit 0 1 interfaces
psb 2170 interfaces preliminary data sheet 90 10.99 figure 56 ssdi interface - active pulse selection figure 57 shows the timing for the ssdi receiver. figure 57 ssdi interface - receiver timing table 53 shows the registers used for configuration of the ssdi interface. table 53 ssdi interface register register # of bits name comment sdchn1 4 nas number of active drst strobe fsc drst active pulse (n=3) fsc 125 s drst dcl dd/dr bit 15 bit 14 bit 1 bit 0
psb 2170 interfaces preliminary data sheet 91 10.99 4.3 analog front end interface the uses a four wire interface similar to the iom ? -2 interface to exchange information with the analog front end (psb 4851). the main difference is that all timeslots and the channel assignments are fixed as shown in figure 58. the is master of this interface and provides afefs as well as afeclk. . figure 58 analog front end interface - frame structure voice data is transferred in 16 bit linear coding in two bidirectional channels c 1 and c 2 . an auxiliary channel c 3 is used to transfer the current setting of the loudspeaker amplifier als to the . the remaining bits are fixed to zero. in the other direction c 3 transfers an override value for als from the to the psb 4851. an additional override bit ov determines if the currently transmitted value should override the aoar:lsc 1) setting. the aoar:lsc setting is not affected by c 3 :als override. table 54 shows the source control of the gain for the als amplifier. furthermore the afe interface can be enabled or disabled according to table 55. 1) see specification of psb 4851 table 54 control of als amplifier aopr:ovre c 3 :ov gain of als amplifier 0 - aoar:lsc 1 0 aoar:lsc 11c 3 :als table 55 analog front end interface register register # of bits name comment afectl 1 en interface enable channel c 1 channel c 3 channel c 2 afefs afedd 125 s als afedu unused 000ov 16 bit 16 bit 8 bit 1 interfaces
psb 2170 interfaces preliminary data sheet 92 10.99 figure 59 analog front end interface - frame start figure 59 shows the synchronization of a frame by afefs. the first clock of a new frame (t 1 ) is indicated by afefs switching from low to high before the falling edge of t 1 . afefs may remain high during subsequent cycles up to t 32 . please see also chapter 3.6.2 for additional information on the frame synchronization. figure 60 analog front end interface - data transfer the data is shifted out with the rising edge of afeclk and sampled at the fa lling edge of afeclk (figure 60). if aopr:ovre is not set, the channel c 3 is not used by the psb 4851. all values (c 1 , c 2 , c 3 :als) are transferred msb first. the data clock (afeclk) rate is fixed at 6.912 mhz. table 56 shows the clock cycles used for the three channels. table 56 analog front end interface clock cycles clock cycles afedd (driven by ) afedu (driven by psb 4851) t 1 -t 16 c 1 data c 1 data t 17 -t 32 c 2 data c 2 data t 33 -t 40 c 3 data c 3 data t 41 -t 864 0tristate afeclk afefs t 1 t 2 afeclk t 1 t 2 afedd afedu bit 0 bit 1 bit 2 bit 0 bit 1 bit 2
psb 2170 interfaces preliminary data sheet 93 10.99 4.4 serial control interface the serial control interface (sci) uses four lines: sdr, sdx, sclk and cs . data is transferred by the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning of an access. data is sampled by the at the rising edge of sclk and shifted out at the falling edge of sclk. each access must be terminated by a rising edge of cs . the accesses to the can be divided into four classes: 1. configuration read/write 2. register read/write 3. status/data read 4. status/data read with interrupt acknowledge if the is in power down mode, a read access to the status register does not deliver valid data with the exception of the rdy bit (rdy=0). after the status has been read the access can be either terminated or extended to read data from the . a register read/write access can only be performed when the is ready. the rdy bit in the status register provides this information. any access to the starts with the transfer of 16 bits to the over line sdr. this first word specifies the access class, access type (read or write) and, if necessary, the register accessed. two access types terminate after the first word: configuration register write and register read. if the configuration register is written, the first word also includes the data and the access is terminated. after an access register read, an access of type data read is necessary to obtain the register data. however, the data is valid only when status:rdy=1. with a second word, all accesses beside configuration register write and register read deliver the status register from the via line sdx. after the second word, the access status register read terminates while all other accesses transfer data with a third word and terminate then. figures 63 to 61 show the timing diagrams for the different access classes and types to the . 1 interfaces
psb 2170 interfaces preliminary data sheet 94 10.99 figure 61 configuration register read access configuration registers at even adresses use bit positions d 7 -d 0 while configuration registers at odd adresses use bit positions d 15 -d 8 . figure 62 configuration register write access or register read command cs sclk sdr c 15 c 14 c 1 c 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for configuration register read : status register : d 15 ,..,d 0 : data to be read : s 15 s 14 s 1 s 0 d 15 d 14 d 1 d 0 cs sclk sdr c 15 c 14 c 1 c 0 c 15 ,..,c 0 : command word for configuration register write : or register read :
psb 2170 interfaces preliminary data sheet 95 10.99 figure 63 status register read access figure 64 data read access cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for status register read : status register : int cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for data read : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be read :
psb 2170 interfaces preliminary data sheet 96 10.99 figure 65 register write access for all commands the external signal int is deactivated as long as the chip is selected (cs is low). for a detailed discussion about the behavior of the interrupt signal please see chapter 3.3. table 57 shows the formats of the different command words. all other command words are reserved. note that interrupts are only acknowledged (cleared) if the command read status/data with interrupt acknowledge is issued. in case of a configuration register write, w determines what configuration register is to be written (table 58): table 57 command words for register access 1514131211109876543210 read status register or data read access (interrupt acknowledge) 0011000000000000 read status register or data read access 1) 1) does not acknowledge interrupt. 1001000000000000 read register 1) 0101 reg write register 1) 0100 reg read configuration reg.011100r000000000 write configuration reg. 0 1 1 0 0 0 w data cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for register write : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be written :
psb 2170 interfaces preliminary data sheet 97 10.99 in case of a configuration register read, r determines what pair of configuration registers is to be read (table 59): note: reading any register except the status register or a hardware configuration register requires at least two accesses. the first access is a register read command (figure 62). with this access the register address is transferred to the . after that access data read accesses (figure 64) must be executed. the first data read access with status:rdy=1 delivers the value of the register. table 58 address field w for configuration register write 9 8 register 0 0 hwconfig 0 0 1 hwconfig 1 1 0 hwconfig 2 1 1 hwconfig 3 table 59 address field r for configuration register read 9 register pair 0 hwconfig 0 / hwconfig 1 1 hwconfig 2 / hwconfig 3
psb 2170 interfaces preliminary data sheet 98 10.99 4.5 general purpose parallel port the provides a general purpose parallel port (gp 0 to gp 15 ). the general purpose parallel port has two modes: static mode and multiplex mode. in both modes, the can generate an interrupt on specific input pins and specific signal edges. each input pin can be masked individually. the events that generated an interrupt are collected in a hold register. table 60 shows the registers for mode selection. 4.5.1 static mode in static mode all pins of the general purpose parallel port interface have identical functionality. any pin can be configured as an output or an input. pins configured as outputs provide a static signal as programmed by the controller. pins configured as inputs are monitoring the signal continuously without latching. the controller always reads the current value. table 61 shows the registers used for static mode. 4.5.2 multiplex mode in multiplex mode, the multiplexes either four output registers or three output register and one input to gp 0 -gp 11. for this, gp 12 -gp 15 are used to distinguish four timeslots. each timeslot has a duration of approximately 2 ms. the timeslots are separated by a gap of approximately 125 s, in which none of the signals gp 12 -gp 15 are active. the multiplexes three output registers to gp 0 -gp 11 in timeslots 0, 1 and 2. in timeslot 3, the direction of the pins can be programmed. for input pins, the signal is latched with the falling edge of gp 12 . table 62 shows the registers used for multiplex mode. this mode is useful for scanning keys or controlling seven segment led displays. table 60 general purpose parallel port mode registers register name comment hwconfig1 app mode selection (static/multiplex) table 61 static mode registers register # of bits comment dout3 16 output signals (for pins configured as outputs) din 16 input signals (for pins configured as inputs) ddir 16 pin direction 1 interfaces
psb 2170 interfaces preliminary data sheet 99 10.99 figure 66 shows the timing diagram for multiplex mode. figure 66 general purpose parallel port - multiplex mode note: in either mode the voltage at any pin (gp 0 to gp 15 ) must not exceed v dd. 4.5.3 interrupt generation for each pin configured as an input, the compares the current value to the previous value. in static mode, the previous value is the value 1.5 ms ago (static mode). in multiplex mode, the previous value is the value sampled during the previous input timeslot. in both modes, the exact sampling point cannot be defined. for a reliable detection of a specific value, it is therefore necessary that a value must be stable at least 2 ms (static mode) or 8 ms (multiplex mode). table 62 multiplex mode registers register # of bits comment dout0 12 output signals on gp 0 -gp 11 while gp 15 =1 dout1 12 output signals on gp 0 -gp 11 while gp 14 =1 dout2 12 output signals on gp 0 -gp 11 while gp 13 =1 dout3 12 output signals (for pins configured as outputs) while gp 12 =1 din 12 input signals (for pins configured as inputs) at fa lling edge of gp 12 ddir 12 pin direction during gp 12 =1 2 ms ma 15 ma 14 ma 13 ma 12 ma 0 -ma 11 dout0 dout2 dout1 dout0 din/dout3
psb 2170 interfaces preliminary data sheet 100 10.99 for each input pin the can be programmed to detect the following changes individually (table 63). whenever an input pin meets the specified condition then the sets the corresponding bit within the register dhold and also the ipp bit of the status register. therefore the register dhold collects all input pins that have met the programmed condition while the status register collects all events at any pin. the change of bit status:ppi can also trigger an external interrupt depending on the mask register intm. the bit status:ipp is reset when the register dhold is read by the controller. the register dhold is also cleared at this time (i.e. when it is read). note: the edge detection can be stopped by writing 0 to the register dhold. writing any other value to dhold starts the edge detection according to the programmed masks. edge detection must be started after a wake-up as it is disabled by default. table 63 interrupt mask definition for parallel port dmask1 dmask2 prev. value cur. value remark 0 0 - - disabled 0 1 0 1 rising edge 1 0 1 0 falling edge 1 1 0 (1) 1 (0) both edges
psb 2170 detailed register description preliminary data sheet 101 10.99 5 detailed register description the has a single status register (read only) and an array of data registers (read/write). the purpose of the status register is to inform the external microcontroller of important status changes of the and to provide a handshake mechanism for data register reading or writing. if the generates an interrupt, the status register contains the reason of the interrupt. 5.1 status register rdy ready rdy ready 0: the last command (if any) is still in progress. 1: the last command has been executed. abt abort 0: no exception during operation 1: an exception caused the to abort any operation currently in progress. the abt bit is cleared by writing the revision register. no other command is accepted by the while abt is set. cia caller id available 0: no new data for caller id 1: new caller id byte available cd carrier detect 0: no carrier detected 1: carrier detected cpt call progress tone 0: currently no call progress tone detected or pause detected (raw mode) 1: currently a call progress tone is detected utd universal tone detected 0: currently no tone is being detetced 15 0 rdy abt 0 0 cia cd cpt utd 0000dtvatvtg0ppi
psb 2170 detailed register description preliminary data sheet 102 10.99 1: currently a tone is being detected dtv dtmf tone valid 0: no new dtmf code available 1: new dtmf code available in ddctl atv alert tone valid 0: no new alert tone code available 1: new alert tone code available in atdctl0 tg tone generator status 0: tone generator not running 1: tone generator running ppi parallel port interrupt 0: no unmasked change at input ports of parallel port 1: at least one unmasked input has changed at the parallel port 5.2 hardware configuration registers hwconfig 0 - hardware configuration register 0 ppsdx push/pull for sdx 0: the sdx pin has open-drain characteristic 1: the sdx pin has push/pull characteristic ppint push/pull for int 0: the int pin has open-drain characteristic 1: the int pin has push/pull characteristic ppsdi push/pull for sdi interface 0: the du and dd pins have open-drain characteristic 1: the du and dd pins have push/pull characteristic 7 0 pd acs 0 0 ppsdi 0 ppint ppsdx
psb 2170 detailed register description preliminary data sheet 103 10.99 acs afe clock source 0: afeclk is derived from the main oscillator 1: afeclk is derived from the clk input pd power down (read only) 0: the is in active mode 1: the is in power down mode
psb 2170 detailed register description preliminary data sheet 104 10.99 hwconfig 1 - hardware configuration register 1 gpp general purpose parallel port act afe clock tracking 0: afeclk tracking disabled 1: afeclk tracking enabled mfs master frame sync selection 0: afefsc 1: fsc xtal xtal frequency ssdi ssdi interface selection 0: iom ? -2 interface 1: ssdi interface 7 0 gpp act ads mfs xtal ssdi 76description 00reserved 0 1 app static mode 1 0 app multiplex mode 11reserved 2 1 factor p 1) 1) the factor p is needed to calculate the clock frequency at afeclk. description 0 0 5 34.560 mhz 0 1 4.5 31.104 mhz 1 0 4 27.648 mhz 1 1 reserved reserved
psb 2170 detailed register description preliminary data sheet 105 10.99 hwconfig 2 - hardware configuration register 2 esdx edge select for dx 0: dx is transmitted with the rising edge of dcl 1: dx is transmitted with the falling edge of dcl esdr edge select for dr 0: dr is latched with the falling edge of dcl 1: dr is latched with the rising edge of dcl 7 0 0 esdx esdr 0 0 0 00
psb 2170 detailed register description preliminary data sheet 106 10.99 hwconfig 3 - hardware configuration register 3 cm1 clock master 1 0: clock and fs generation at afeclk and afefs disabled 1: clock and fs generation at afeclk and afefs enabled cm0 clock master 0 0: 512 khz (afeclk) 1: 1.536 mhz (afeclk) 7 0 000000cm1cm0
psb 2170 detailed register description preliminary data sheet 107 10.99 00h rev revision...................................................................... 111 01h r cctl chip control ............................................................... 112 02h r intm interrupt mask register .............................................. 113 03h r afectl analog front end interface control............................ 114 04h r ifs1 interface select 1 ....................................................... 115 05h r ifg1 interface gain 1.......................................................... 116 06h r ifg2 interface gain 2.......................................................... 117 07h r ifs2 interface select 2 ....................................................... 118 08h r ifg3 interface gain 3.......................................................... 119 09h r ifg4 interface gain 4.......................................................... 120 0ah r sdconf serial data interface configuration ............................ 121 0bh r sdchn1 serial data interface channel 1 ................................. 122 0ch r ifs3 interface select 3 ....................................................... 124 0dh r sdchn2 serial data interface channel 2 ................................. 125 0eh r ifs4 interface select 4 ....................................................... 126 0fh r ifg5 interface gain 5.......................................................... 127 10h r ua universal attenuator................................................... 128 11h r dgctl dtmf generator control............................................ 129 12h dgf1 dtmf generator frequency 1 ................................... 130 13h dgf2 dtmf generator frequency 2 ................................... 131 14h dgl dtmf generator level............................................... 132 15h dgatt dtmf generator attenuation ..................................... 133 1ah r atdctl0 alert tone detection 0................................................ 134 1bh atdctl1 alert tone detection 1................................................ 135 1ch r cidctl0 caller id control 0...................................................... 136 1dh cidctl1 caller id control 1...................................................... 137 1eh r ifs5 interface select 5 ....................................................... 138 1fh r ifg6 interface gain 6.......................................................... 139 20h r cptctl call progress tone control ........................................ 140 21h cpttr call progress tone thresholds.................................. 141 22h cptmn cpt minimum times.................................................. 142 23h cptmx cpt maximum times................................................. 143 24h cptdt cpt delta times ........................................................ 144 25h r lecctl line echo cancellation control .................................. 145 26h leclev minimal signal level for line echo cancellation ....... 146 27h lecatt externally provided attenuation ................................. 147 28h lecmgn margin for double talk detection............................... 148 29h r ddctl dtmf detector control .............................................. 149 2ah ddtw dtmf detector signal twist ...................................... 150 2bh ddlev dtmf detector minimum signal level....................... 151 2ch r fcfctl1 equalizer 1 control..................................................... 152 2dh fcfcof1 equalizer 1 coefficient data....................................... 154 2eh r fcfctl2 equalizer 2 control..................................................... 155 detailed register description
psb 2170 detailed register description preliminary data sheet 108 10.99 2fh fcfcof2 equalizer 2 coefficient data........................................157 30h r tgctl tone generator control ..............................................158 31h tgton tone generator time ton .........................................159 32h tgtoff tone generator time toff .......................................160 33h tgt1 tone generator time t1.............................................161 34h tgf1 tone generator frequency f1....................................162 35h tgg1 tone generator gain g1 ............................................163 36h tgt2 tone generator time t2.............................................164 37h tgf2 tone generator frequency f2....................................165 38h tgg2 tone generator gain g2 ............................................166 39h tgt3 tone generator time t3.............................................167 3ah tgf3 tone generator frequency f3....................................168 3bh tgg3 tone generator gain g3 ............................................169 3ch tgf4 tone generator frequency f4....................................170 3dh tgg4 tone generator gain g4 ............................................171 3eh tggo1 tone generator gain output 1 ...................................172 3fh tggo2 tone generator gain output 2 ...................................173 45h r pdctl peak detector control.................................................174 46h pddata peak detector data.....................................................175 47h r spsctl sps control ................................................................176 4ah dout0 data out (timeslot 0) ..................................................177 4bh dout1 data out (timeslot 1) ..................................................178 4ch dout2 data out (timeslot 2) ..................................................179 4dh dout3 data out (timeslot 3 or static mode)..........................180 4eh din data in (timeslot 3 or static mode) ............................181 4fh ddir data direction (timeslot 3 or static mode) .................182 50h dmask1 data in mask 1 (timeslot 3 or static mode)................183 51h dmask2 data in mask 2 (timeslot 3 or static mode)................184 52h r dhold data in hold (timeslot 3 or static mode) ....................185 58h r agcctl agc control................................................................186 59h agcatt automatic gain control attenuation............................187 5ah agc1 automatic gain control 1 ............................................188 5bh agc2 automatic gain control 2 ............................................189 5ch agc3 automatic gain control 3 ............................................190 5dh agc4 automatic gain control 4 ............................................191 5eh agc5 automatic gain control 5 ............................................192 60h r sctl speakerphone control ................................................193 62h r ssrc1 speakerphone source 1 .............................................195 63h r ssrc2 speakerphone source 2 .............................................196 64h ssdx1 speech detector (transmit) 1 .....................................197 65h ssdx2 speech detector (transmit) 2 .....................................198 66h ssdx3 speech detector (transmit) 3 .....................................199 67h ssdx4 speech detector (transmit) 4 .....................................200
psb 2170 detailed register description preliminary data sheet 109 10.99 68h ssdr1 speech detector (receive) 1 ..................................... 201 69h ssdr2 speech detector (receive) 2 ..................................... 202 6ah ssdr3 speech detector (receive) 3 ..................................... 203 6bh ssdr4 speech detector (receive) 4 ..................................... 204 6ch sscas1 speech comparator (acoustic side) 1 ....................... 205 6dh sscas2 speech comparator (acoustic side) 2 ....................... 206 6eh sscas3 speech comparator (acoustic side) 3 ....................... 207 6fh sscls1 speech comparator (line side) 1.............................. 208 70h sscls2 speech comparator (line side) 2.............................. 209 71h sscls3 speech comparator (line side) 3.............................. 210 72h satt1 attenuation unit 1....................................................... 211 73h satt2 attenuation unit 2....................................................... 212 74h sagx1 automatic gain control (transmit) 1.......................... 213 75h sagx2 automatic gain control (transmit) 2.......................... 214 76h sagx3 automatic gain control (transmit) 3.......................... 215 77h sagx4 automatic gain control (transmit) 4.......................... 216 78h sagx5 automatic gain control (transmit) 5.......................... 217 79h sagr1 automatic gain control (receive) 1........................... 218 7ah sagr2 automatic gain control (receive) 2........................... 219 7bh sagr3 automatic gain control (receive) 3........................... 220 7ch sagr4 automatic gain control (receive) 4........................... 221 7dh sagr5 automatic gain control (receive) 5........................... 222 7eh slga line gain .................................................................... 223 7fh saelen acoustic echo cancellation length............................ 224 80h saeaw acoustic echo cancellation adaptation window........ 225 81h saeel acoustic echo cancellation reported attenuation limit......................................................... 226 82h saedtr acoustic echo cancellation double talk reduction ................................................................... 227 83h saedtl acoustic echo cancellation double talk limit ........... 228 84h saedti acoustic echo cancellation double talk increment ................................................................... 229 85h saedtd acoustic echo cancellation double talk decrement.................................................................. 230 86h saewfl wiener filter limit attenuation ................................... 231 87h snratt noise reduction attenuation...................................... 232 88h snrlnl noise reduction lower noise limit ........................... 233 89h snrunl noise reduction upper noise limit ........................... 234 90h scsd1 speech detector (comfort noise) 1 ........................... 235 91h scsd2 speech detector (comfort noise) 2 ........................... 236 92h scsd3 speech detector (comfort noise) 3 ........................... 237 93h scsd4 speech detector (comfort noise) 4 ........................... 238 94h sclpt low pass time constant ........................................... 239
psb 2170 detailed register description preliminary data sheet 110 10.99 95h sccr correlation...................................................................240 96h sccrn correlation noise threshold .......................................241 97h sccrs correlation sensitivity .................................................242 98h sccrl correlation limit ..........................................................243 99h scdtn double talk detection threshold................................244 9ah scdts double talk sensitivity................................................245 9bh scdtl double talk limit ........................................................246 9ch scattn attenuation noise ........................................................247 9dh scatts attenuation sensitivity.................................................248 9eh scattl attenuation limit .........................................................249 9fh sclspn loudspeaker noise .....................................................250 a0h sclsps loudspeaker sensitivity ..............................................251 a1h sclspl loudspeaker limit.......................................................252 a2h sccn1 comfort noise constant level ....................................253 a3h sccn2 comfort noise multiplication factor ............................254 a4h sccn3 comfort noise low pass.............................................255 a6h r nrctl noise reduction control .............................................256 a7h nratt noise reduction attenuation.......................................257 a8h r utdctl universal tone detector control.................................258 a9h utdcf center frequency for utd..........................................259 aah utdbw band width for utd ....................................................260 abh utdlim limiter limit for utd ...................................................261 ach utdlev minimal signal level for utd......................................262 adh utddlt minimum difference for utd.......................................263 aeh utdtmt tone times for utd....................................................264 afh utdtmg gap times for utd .....................................................265 b0h r cidmf1 caller id message format ..........................................267 b1h r cidmf2 caller id message format ..........................................268 b2h r cidmf3 caller id message format ..........................................269 b3h r cidmf4 caller id message format ..........................................270 b4h r cidmf5 caller id message format ..........................................271 b5h r cidmf6 caller id message format ..........................................272
psb 2170 detailed register description preliminary data sheet 111 10.99 00 h rev revision the revision register can be read only. note: a write access to the revision register does not change its content. it does, however, clear the abt bit of the status register. 15 0 0011001100000000 detailed register description
psb 2170 detailed register description preliminary data sheet 112 10.99 01 h r cctl chip control pd power down 0: is in active mode 1: enter power-down mode 15 0 0000000pd00000000 reset value 0000000000000000
psb 2170 detailed register description preliminary data sheet 113 10.99 02 h r intm interrupt mask register if a bit of this register is reset (set to 0), the corresponding bit of the status register does not generate an interrupt. if a bit is set (set to 1), an external interrupt can be generated by the corresponding bit of the status register. 15 0 rdy 1 0 0 cia cd cpt utd 0000dtvatvtg0ppi reset value 0100000000000000
psb 2170 detailed register description preliminary data sheet 114 10.99 03 h r afectl analog front end interface control als loudspeaker amplification this value is transferred on channel c3 of the afe interface. if the psb 4851 is used it represents the amplification of the loudspeaker amplifier. en interface enable 0: afe interface disabled 1: afe interface enabled 15 0 0000 als 0000000en reset value 0000 0 00000000
psb 2170 detailed register description preliminary data sheet 115 10.99 04 h r ifs1 interface select 1 the signal selection fields i1, i2 and i3 of ifs1 determine the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. hp high-pass for s 1 0: disabled 1: enabled i1 input signal 1 for ig2 i2 input signal 2 for ig2 i3 input signal 3 for ig2 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 2170 detailed register description preliminary data sheet 116 10.99 05 h r ifg1 interface gain 1 ifg1 is associated with the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. ig1 in order to obtain a gain g the parameter ig1 can be calculated by the following formula: 15 0 0ig1 reset value 0 8192 (0 db) ig1 32768 g 12.04 db ? () 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 117 10.99 06 h r ifg2 interface gain 2 ifg2 is associated with the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. ig2 gain of amplifier ig2 in order to obtain a gain g the parameter ig2 can be calculated by the following formula: 15 0 0ig2 reset value 0 8192 (0 db) ig2 32768 g 12.04 db ? () 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 118 10.99 07 h r ifs2 interface select 2 the signal selection fields i1, i2 and i3 of ifs2 determine the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. the hp bit enables a high-pass for the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. hp high-pass for s 3 0: disabled 1: enabled i1 input signal 1 for ig4 i2 input signal 2 for ig4 i3 input signal 3 for ig4 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 2170 detailed register description preliminary data sheet 119 10.99 08 h r ifg3 interface gain 3 ifg3 is associated with the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. ig3 gain of amplifier ig3 in order to obtain a gain g the parameter ig3 can be calculated by the following formula: 15 0 0ig3 reset value 0 8192 (0 db) ig3 32768 g 12.04 db ? () 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 120 10.99 09 h r ifg4 interface gain 4 ifg4 is associated with the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. ig4 gain of amplifier ig4 in order to obtain a gain g the parameter ig4 can be calculated by the following formula: 15 0 0ig4 reset value 0 8192 (0 db) ig4 32768 g 12.04 db ? () 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 121 10.99 0a h r sdconf serial data interface configuration nts number of timeslots dcl double clock mode 0: single clock mode 1: double clock mode en enable interface 0: interface is disabled (both channels) 1: interface is enabled (depending on separate channel enable bits) 15 0 00 nts 00000dcl0en reset value 00 0 00000000 11 10 9 8 7 6 description 0000001 0000012 ... ... ... ... ... ... ... 11111164
psb 2170 detailed register description preliminary data sheet 122 10.99 0b h r sdchn1 serial data interface channel 1 nas number of active drst strobe (ssdi interface mode) pcd pcm code 0: a-law 1: -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, du: data downstream ts timeslot for channel 1 15 0 nas 0 0 pcd en pcm dd ts reset value 0 000000 0 15 14 13 12 description 00001 ... ... ... ... ... 111116 543210description 0000000 ... ... ... ... ... ... ... 11111163
psb 2170 detailed register description preliminary data sheet 123 10.99 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case.
psb 2170 detailed register description preliminary data sheet 124 10.99 0c h r ifs3 interface select 3 the signal selection fields i1, i2 and i3 of ifs3 determine the outgoing signal of channel 1 of the iom ? -2/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog iom ? - 2/ssdi-interface. hp high-pass for s 5 0: disabled 1: enabled i1 input signal 1 for s 6 i2 input signal 2 for s 6 i3 input signal 3 for s 6 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 2170 detailed register description preliminary data sheet 125 10.99 0d h r sdchn2 serial data interface channel 2 cs channel split 0: single 16 bit or single 8 bit channel 1: two adjacent 8 bit channels (sdchn2:pcm must be set to 0) pcd pcm code 0: a-law 1: -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, dd: data downstream ts timeslot for channel 2 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case. 15 0 cs00000pcdenpcmdd ts reset value 0000000000 0 543210description 0000000 0000011 ... ... ... ... ... ... ... 11111163
psb 2170 detailed register description preliminary data sheet 126 10.99 0e h r ifs4 interface select 4 the signal selection fields i1, i2 and i3 of ifs4 determine the outgoing signal of channel 2 of the iom ? -2/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 2 of the iom ? -2/ssdi interface. hp high-pass for s 7 0: disabled 1: enabled i1 input signal 1 for s 8 i2 input signal 2 for s 8 i3 input signal 3 for s 8 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 2170 detailed register description preliminary data sheet 127 10.99 0f h r ifg5 interface gain 5 att1 attenuation for i3 (channel 1) in order to obtain an attenuation a at i3 of channel 1 of the iom ? -2/ssdi interface, the parameter att1 can be calculated by the following formula: att2 attenuation for i3 (channel 2) in order to obtain an attenuation a at i3 of channel 2 of the iom ? -2/ssdi interface, the parameter att2 can be calculated by the following formula: 15 0 att1 att2 reset value 255 (0 db) 255 (0 db) att1 256 a20db ? 10 = att2 256 a20db ? 10 =
psb 2170 detailed register description preliminary data sheet 128 10.99 10 h r ua universal attenuator att attenuation for ua for a given attenuation a [db] the parameter att can be calculated by the following formula: i1 input selection for ua 15 0 att 000 i1 reset value 0 (96db) 000 0 att 256 a ? 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 129 10.99 11 h r dgctl dtmf generator control en generator enable 0: disabled 1: enabled md mode 0: raw 1: cooked dtc dial tone code (cooked mode) 15 0 enmd0000000000 dtc reset value 000000000000 0 3 2 1 0 digit frequency 0 0 0 0 1 697/1209 0 0 0 1 2 697/1336 0 0 1 0 3 697/1477 0 0 1 1 a 697/1633 0 1 0 0 4 770/1209 0 1 0 1 5 770/1336 0 1 1 0 6 770/1477 0 1 1 1 b 770/1633 1 0 0 0 7 852/1209 1 0 0 1 8 852/1336 1 0 1 0 9 852/1477 1 0 1 1 c 852/1633 1 1 0 0 * 941/1209 1 1 0 1 0 941/1336 1 1 1 0 # 941/1477 1 1 1 1 d 941/1633
psb 2170 detailed register description preliminary data sheet 130 10.99 12 h dgf1 dtmf generator frequency 1 frq frequency of generator 1 the parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0frq frq 32768 f 4000hz -------------------- - =
psb 2170 detailed register description preliminary data sheet 131 10.99 13 h dgf2 dtmf generator frequency 2 frq frequency of generator 2 he parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0frq frq 32768 f 4000hz -------------------- - =
psb 2170 detailed register description preliminary data sheet 132 10.99 14 h dgl dtmf generator level lev2 signal level of generator 2 in order to obtain a signal level l (relative to the pcm maximum value) for generator 2 the value of lev2 can be calculated according to the following formula: lev1 signal level of generator 1 in order to obtain a signal level l (relative to the pcm maximum value) for generator 1 the value of lev1 can be calculated according to the following formula: 15 0 0lev20lev1 lev2 128 l20db ? 10 = lev1 128 l20db ? 10 =
psb 2170 detailed register description preliminary data sheet 133 10.99 15 h dgatt dtmf generator attenuation att2 attenuation of signal s 10 in order to obtain attenuation a the parameter att2 can be calculated by the formula: att1 attenuation of signal s 9 in order to obtain attenuation a the parameter att1 can be calculated by the formula: 15 0 att2 att1 att2 128 1024 a ? 20 db ? 10 + a181db , > ; 128 a ? 20 db ? 10 a181db , < ; ? ? ? = att1 128 1024 a ? 20 db ? 10 + a181db , > ; 128 a ? 20 db ? 10 a181db , < ; ? ? ? =
psb 2170 detailed register description preliminary data sheet 134 10.99 1a h r atdctl0 alert tone detection 0 en enable alert tone detection 0: the alert tone detection is disabled 1: the alert tone detection is enabled i1 input signal selection atc alert tone code 15 0 en00 i1 000000 atc reset value 000 0 000000 - 1) 1) undefined 10 description 0 0 no tone 0 1 2130 1 0 2750 1 1 2130/2750
psb 2170 detailed register description preliminary data sheet 135 10.99 1b h atdctl1 alert tone detection 1 md alert tone detection mode 0: only a dual tone is detected 1: either a dual or a single tone is detected dev maximum frequency deviation for alert tone 0: 0.5% 1: 1.1% onh on hook 0: off hook 1: on hook min minimum level of alert tone signal for a minimum signal level min the parameter min is given by the following formula: 15 0 md00dev000onh min min 2560 min 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 136 10.99 1c h r cidctl0 caller id control 0 en cid enable 0: disabled 1: enabled dot drop out tolerance 0: drop out during mark or seizure sequence aborts recognition 1: drop out tolerance during mark or seizure sequence. cm compatibilitiy mode 0: standard caller id decoder 1: improved caller id decoder (bellcore compliant) i1 input signal selection data last received data byte 15 0 en dot cm i1 data reset value 000 0 0
psb 2170 detailed register description preliminary data sheet 137 10.99 1d h cidctl1 caller id control 1 nmb minimum number of mark bits nmss minimum number of mark/space sequences min minimum signal level for cid decoder for a minimum signal level min the parameter min is given by the following formula: 15 0 nmb nmss min 15 14 13 12 11 description 000000 0000110 0001020 ... ... ... ... ... ... 11111310 109876description 000001 0000111 0001021 ... ... ... ... ... 11111311 min 640 min 20 db ? 10 =
psb 2170 detailed register description preliminary data sheet 138 10.99 1e h r ifs5 interface select 5 the signal selection fields i1, i2 and i3 of ifs5 determine the outgoing signal of channel 3 of the iom/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 3. hp high-pass for s 23 0: disabled 1: enabled i1 input signal 1 for s 24 i2 input signal 2 for s 24 i3 input signal 3 for s 24 as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 2170 detailed register description preliminary data sheet 139 10.99 1f h r ifg6 interface gain 6 att3 attenuation for i3 (channel 3) in order to obtain an attenuation a the parameter att3 can be calculated by the following formula: 15 0 att3 00000000 reset value 255 (0db) 00000000 att3 256 a20db ? 10 =
psb 2170 detailed register description preliminary data sheet 140 10.99 20 h r cptctl call progress tone control en cpt detector enable 0: disabled 1: enabled md cpt mode 0: raw 1: cooked i1 input signal selection 15 0 enmd000000000 i1 reset value 00000000000 0
psb 2170 detailed register description preliminary data sheet 141 10.99 21 h cpttr call progress tone thresholds num number of cycles sn minimal signal-to-noise ratio min minimum signal level for cpt detector 15 0 num 0 sn min 15 14 13 cooked mode raw mode 0 0 0 reserved 0 0 0 1 2 reserved ... ... ... ... reserved 1 1 1 8 reserved 11 10 9 8 description 11119db 100012db 010015db 001018db 000022db value description 64 h -30 db 60 h -32 db 7a h -34 db 74 h -36 db 70 h -38 db 89 h -40 db 85 h -42 db 80 h -44 db 9a h -46 db 95 h -48 db 90 h -50 db
psb 2170 detailed register description preliminary data sheet 142 10.99 22 h cptmn cpt minimum times minb minimum time for cpt burst the parameter minb for a minimal burst time tbmin can be calculated by the following formula: ming minimum time for cpt gap the parameter ming for a minimal gap time tgmin can be calculated by the following formula: 15 0 minb ming minb tbmin 32 ms ? 4 --------------------------------------- - = ming tgmin 32 ms ? 4 ---------------------------------------- - =
psb 2170 detailed register description preliminary data sheet 143 10.99 23 h cptmx cpt maximum times maxb maximum time for cpt burst the parameter maxb for a maximal burst time of tbmax can be calculated by the following formula: maxg maximum time for cpt gap the parameter maxg for a maximal burst time of tgmax can be calculated by the following formula: 15 0 maxb maxg maxb tbmax tbmin ? 8 ------------------------------------------ - = maxg tgmax tgmin ? 8 ------------------------------------------- - =
psb 2170 detailed register description preliminary data sheet 144 10.99 24 h cptdt cpt delta times difb maximum time difference between consecutive bursts the parameter difb for a maximal difference of t ms of two burst durations can be calculated by the following formula: difg maximum time difference between consecutive gaps the parameter difg for a maximal difference of t ms of two gap durations can be calculated by the following formula: 15 0 difb difg difb t 2ms ------------ - = difg t 2ms ------------ - =
psb 2170 detailed register description preliminary data sheet 145 10.99 25 h r lecctl line echo cancellation control en enable 0: disabled 1: enabled cm line echo canceller mode as adaptation stop 0: adation enabled 1: adation stopped sp adaptation speed 0: fast adaptation (extended mode only) 1: slow adaptation (extended mode only) i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 en cm as sp 0 i1 i2 reset value 0 0 000 0 0 14 13 line echo canceller mode 0 0 normal mode 0 1 superior mode 1 0 extended mode 11reserved
psb 2170 detailed register description preliminary data sheet 146 10.99 26 h leclev minimal signal level for line echo cancellation min the parameter min for a minimal signal level l (db) can be calculated by the following formula: 15 0 0min min 512 96.3 l + () 5log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 147 10.99 27 h lecatt externally provided attenuation att the parameter att for an externally provided attenuation a (db) can be calculated by the following formula: att has a slightly different meaning in normal and in superior mode. in normal mode, it represents just the externally provided attenunation while in superior mode, it represents the externally provided attenuation minus a threshold. the formula above holds in both cases. in superior mode, the parameter att is implemented in two ? s complement. in normal mode, the parameter att is not allowed to be negative, i.e., the msb (bit 15) must be 0. 15 0 0att att 512 a 5 log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 148 10.99 28 h lecmgn margin for double talk detection mgn the parameter mgn for a margin of l (db) can be calculated by the following formula: note: mgn has a different meaning in normal and in superior mode. the formula above holds in any mode, though. 15 0 0mgn mgn 512 l 5 log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 149 10.99 29 h r ddctl dtmf detector control en enable dtmf tone detection 0: the dtmf detection is disabled 1: the dtmf detection is enabled i1 input signal selection dtc dtmf tone code 15 0 en00 i1 000 dtc 1) 1) the dtc code remains valid until a new dtmf tone has been detected. reset value 000 0 000 - 2) 2) undefined 4 3 2 1 0 frequency digit 1 0 0 0 0 941 / 1633 d 1 0 0 0 1 697 / 1209 1 1 0 0 1 0 697 / 1336 2 1 0 0 1 1 697 / 1477 3 1 0 1 0 0 770 / 1209 4 1 0 1 0 1 770 / 1336 5 1 0 1 1 0 770 / 1477 6 1 0 1 1 1 852 / 1209 7 1 1 0 0 0 852 / 1336 8 1 1 0 0 1 852 / 1477 9 1 1 0 1 0 941 / 1336 0 1 1 0 1 1 941 / 1209 * 1 1 1 0 0 941 / 1477 # 1 1 1 0 1 697 / 1633 a 1 1 1 1 0 770 / 1633 b 1 1 1 1 1 852 / 1633 c
psb 2170 detailed register description preliminary data sheet 150 10.99 2a h ddtw dtmf detector signal twist twist signal twist for dtmf tone in order to obtain a minimal signal twist t the parameter twist can be calculated by the following formula: note: twist must be in the range [4096,20480] 15 0 0twist twist 32768 0.5 db+t () ? () 10 db ? 10 =
psb 2170 detailed register description preliminary data sheet 151 10.99 2b h ddlev dtmf detector minimum signal level min minimum signal level note: values outside the given range are reserved and must not be used. 15 0 1111111111 min 543210 description 001110 -50db 001111 -49db ... ... ... ... ... ... ... 100001 -31db 100010 -30db
psb 2170 detailed register description preliminary data sheet 152 10.99 2c h r fcfctl1 equalizer 1 control en enable equalizer 1 0: the equalizer is disabled 1: the equalizer is enabled adr coefficient address 15 0 en0 adr 000 i1 reset value 00 0 000 0 13 12 11 10 9 8 coefficient 000000 a1 000001 a2 000010 a3 000011 a4 000100 a5 000101 a6 000110 a7 000111 a8 001000 a9 001001 b2 001010 b3 001011 b4 001100 b5 001101 b6 001 110 b7 001111 b8 010000 b9 010001 c1 010010 d1 010011 d2 010100 d3 010101 d4 01 0110 d5
psb 2170 detailed register description preliminary data sheet 153 10.99 i1 input signal selection 010111 d6 011000 d7 011001 d8 011010 d9 011011 d10 011100 d11 011101 d12 01 1 110 d13 011111 d14 100000 d15 100001 d16 100010 d17 100011 c2 13 12 11 10 9 8 coefficient
psb 2170 detailed register description preliminary data sheet 154 10.99 2d h fcfcof1 equalizer 1 coefficient data v coefficient value for the coefficients a 1 -a 9 , b 2 -b 9 and d 1 -d 17 , the following formula can be used, where v denotes the coefficient value of the coefficient c : for the coefficients c 1 and c 2 , the following formula can be used, where v denotes the coefficient value of the coefficient c : 15 0 v v 32768 c = ; -1 c 1 < v128c = ; 1 c 256 <
psb 2170 detailed register description preliminary data sheet 155 10.99 2e h r fcfctl2 equalizer 2 control en enable equalizer 1 0: the equalizer is disabled 1: the equalizer is enabled adr coefficient address 15 0 en0 adr 000 i1 reset value 00 0 000 0 13 12 11 10 9 8 coefficient 000000 a1 000001 a2 000010 a3 000011 a4 000100 a5 000101 a6 000110 a7 000111 a8 001000 a9 001001 b2 001010 b3 001011 b4 001100 b5 001101 b6 001 110 b7 001111 b8 010000 b9 010001 c1 010010 d1 010011 d2 010100 d3 010101 d4 01 0110 d5
psb 2170 detailed register description preliminary data sheet 156 10.99 i1 input signal selection 010111 d6 011000 d7 011001 d8 011010 d9 011011 d10 011100 d11 011101 d12 0 1 1 1 1 0 d13 011111 d14 100000 d15 100001 d16 100010 d17 100011 c2 13 12 11 10 9 8 coefficient
psb 2170 detailed register description preliminary data sheet 157 10.99 2f h fcfcof2 equalizer 2 coefficient data v coefficient value for the coefficients a 1 -a 9 , b 2 -b 9 and d 1 -d 17 , the following formula can be used, where v denotes the coefficient value of the coefficient c : for the coefficients c 1 and c 2 , the following formula can be used, where v denotes the coefficient value of the coefficient c : 15 0 v v 32768 c = ; -1 c 1 < v128c = ; 1 c 256 <
psb 2170 detailed register description preliminary data sheet 158 10.99 30 h r tgctl tone generator control cgm control generator mode dt dual tone 0: f4 not added (option 1) 1: f4 added (option 2) bgm beat generator mode sm stop mode 0: immediate 1: controlled wf waveform 0: sine wave 1: square wave 15 0 000000000 cgm dt bgm smwf reset value 000000000 0 0 0 00 65 description 0 0 tone generator off 0 1 tone generator on 1 - tone generator enabled/disabled by control generator 32 description 0 0 continuous tone f1 0 1 continuous tone f2 1 0 two tone cadence 1 1 three tone sequence
psb 2170 detailed register description preliminary data sheet 159 10.99 31 h tgton tone generator time ton tm mantissa of ton the mantissa tm for a time t ([ms]) can be calculated by the following formula: te exponent of ton the exponent te for a time t ([ms]) can be calculated by the following formula: note: te > 0 15 0 tm te tm t 2 te --------- = te log 2 t =
psb 2170 detailed register description preliminary data sheet 160 10.99 32 h tgtoff tone generator time toff tm mantissa of toff the mantissa tm for a time t ([ms]) can be calculated by the following formula: te exponent of toff the exponent te for a time t ([ms]) can be calculated by the following formula: note: te > 0 15 0 tm te tm t 2 te --------- = te log 2 t =
psb 2170 detailed register description preliminary data sheet 161 10.99 33 h tgt1 tone generator time t1 time the parameter time for a time t ([ms]) can be calculated by the following formula: 15 0 time time t 8 -- - =
psb 2170 detailed register description preliminary data sheet 162 10.99 34 h tgf1 tone generator frequency f1 f frequency the parameter f for a frequency f ([hz]) can be calculated by the following formula: note: if a sine waveform is selected, the frequency f is output. if a square waveform is selected the next lower frequency that is a harmonic frequency is output. 15 0 0f f8.192f =
psb 2170 detailed register description preliminary data sheet 163 10.99 35 h tgg1 tone generator gain g1 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 164 10.99 36 h tgt2 tone generator time t2 time the parameter time for a time t ([ms]) can be calculated by the following formula: 15 0 time time t 8 -- - =
psb 2170 detailed register description preliminary data sheet 165 10.99 37 h tgf2 tone generator frequency f2 f frequency the parameter f for a frequency f ([hz]) can be calculated by the following formula: note: if a sine waveform is selected, the frequency f is output. if a square waveform is selected the next lower frequency that is a harmonic frequency is output. 15 0 0f f8.192f =
psb 2170 detailed register description preliminary data sheet 166 10.99 38 h tgg2 tone generator gain g2 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 167 10.99 39 h tgt3 tone generator time t3 time the parameter time for a time t ([ms]) can be calculated by the following formula: 15 0 time time t 8 -- - =
psb 2170 detailed register description preliminary data sheet 168 10.99 3a h tgf3 tone generator frequency f3 f frequency the parameter f for a frequency f ([hz]) can be calculated by the following formula: note: if a sine waveform is selected, the frequency f is output. if a square waveform is selected the next lower frequency that is a harmonic frequency is output. 15 0 0f f8.192f =
psb 2170 detailed register description preliminary data sheet 169 10.99 3b h tgg3 tone generator gain g3 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 170 10.99 3c h tgf4 tone generator frequency f4 f frequency the parameter f for a frequency f ([hz]) can be calculated by the following formula: note: if a sine waveform is selected, the frequency f is output. if a square waveform is selected the next lower frequency that is a harmonic frequency is output. 15 0 0f f8.192f =
psb 2170 detailed register description preliminary data sheet 171 10.99 3d h tgg4 tone generator gain g4 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 172 10.99 3e h tggo1 tone generator gain output 1 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 173 10.99 3f h tggo2 tone generator gain output 2 ggain the parameter g for a gain g ([db]) can be calculated by the following formula: 15 0 0g f 32768 g20 ? 10 =
psb 2170 detailed register description preliminary data sheet 174 10.99 45 h r pdctl peak detector control en peak detector enable 0: disabled 1: enabled mm min/max 0: maximum 1: minimum i1 input signal selection 15 0 enmm000000000 i1 reset value 00000000000 0
psb 2170 detailed register description preliminary data sheet 175 10.99 46 h pddata peak detector data data maximum or minimum value of signal since last read access. note: this register can only be read. 15 0 data
psb 2170 detailed register description preliminary data sheet 176 10.99 47h r spsctl sps control pos position of status register window mode mode of sps interface sp1 direct control for sps 1 0: sps 1 set to 0 1: sps 1 set to 1 sp0 direct control for sps 0 0: sps 0 set to 0 1: sps 0 set to 1 note: if mode 1 has been selected prior to power-down, both mode 1 and the values of sp1 and sp0 are retained during power-down and wake-up. other modes are reset to 0 during power down. 15 0 pos 0000000 mode sp1sp0 reset value 0 0000000 0 - 1) 1) undefined - 1) 15 14 13 12 sps 0 sps 1 0000bit 0 bit 1 0001bit 1 bit 2 ... ... ... ... ... ... 1 1 1 0 bit 14 undefined 4 3 2 description 0 0 0 disabled (sps 0 and sps 1 zero) 0 0 1 output of sp1 and sp0 1 0 0 output of speakerphone state at sp1 and sp0 1 1 0 output of status register at sp1 and sp0
psb 2170 detailed register description preliminary data sheet 177 10.99 4a h dout0 data out (timeslot 0) data output data output data for pins gp 0 -gp 11 while gp 12 =1 (only if hwconfig1:gpp=10). 15 0 0000 data reset value 0000 0
psb 2170 detailed register description preliminary data sheet 178 10.99 4b h dout1 data out (timeslot 1) data output data output data for pins gp 0 -gp 11 while gp 13 =1 (only if hwconfig1:gpp=10). 15 0 0000 data reset value 0000 0
psb 2170 detailed register description preliminary data sheet 179 10.99 4c h dout2 data out (timeslot 2) data output data output data for pins gp 0 -gp 11 while gp 14 =1 (only if hwconfig1:gpp=10). 15 0 0000 data reset value 0000 0
psb 2170 detailed register description preliminary data sheet 180 10.99 4d h dout3 data out (timeslot 3 or static mode) data output data output data for pins gp 0 -gp 11 while gp 15 =1 (only if hwconfig1:gpp=10). output data for pins gp 0 -gp 15 (only if hwconfig1:gpp=01) 15 0 data reset value 0
psb 2170 detailed register description preliminary data sheet 181 10.99 4e h din data in (timeslot 3 or static mode) data input data input data for pins gp 0 -gp 11 at falling edge of gp 12 (only if hwconfig1:gpp=10). input data for pins gp 0 -gp 15 (only if hwconfig1:gpp=01) 15 0 data
psb 2170 detailed register description preliminary data sheet 182 10.99 4f h ddir data direction (timeslot 3 or static mode) dir port direction port direction during gp 12 =1 or in static mode. 0: input 1: output 15 0 dir reset value 0 (all inputs)
psb 2170 detailed register description preliminary data sheet 183 10.99 50 h dmask1 data in mask 1 (timeslot 3 or static mode) mask bit mask for falling edge detection if a bit of the mask is set and the corresponding pin is configured as an input, a falling edge at this input will set the ppi bit of the status register. 15 0 mask
psb 2170 detailed register description preliminary data sheet 184 10.99 51 h dmask2 data in mask 2 (timeslot 3 or static mode) mask bit mask for rising edge detection if a bit of the mask is set and the corresponding pin is configured as an input, a rising edge at this input will set the ppi bit of the status register. 15 0 mask
psb 2170 detailed register description preliminary data sheet 185 10.99 52 h r dhold data in hold (timeslot 3 or static mode) data all events, which were not masked by dmask1 or dmask2 register, are collected in this register since the last read access. whenever this register is read it is reset to zero. a bit is subsequently set if an unmasked event happens at the corresponding input pin. 15 0 data
psb 2170 detailed register description preliminary data sheet 186 10.99 58 h r agcctl agc control en enable 0: disabled 1: enabled i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 en00000 i1 i2 reset value 000000 0 0
psb 2170 detailed register description preliminary data sheet 187 10.99 59 h agcatt automatic gain control attenuation att the parameter att for an attenuation a ([db]) can be calculated by the following formula: 15 0 0att att 32768 a ? 20 ------ - 10 =
psb 2170 detailed register description preliminary data sheet 188 10.99 5a h agc1 automatic gain control 1 com the parameter com for a signal level l ([db]) can be calculated by the following formula: ag_init in order to obtain an initial gain g ([db]) the parameter ag_init can be calculated by the following formula: 15 0 com ag_init com 128 10 + l6622 , + 20 ------------------------- - l -42,14 db < ; 10 l4214 , + 20 ------------------------- - l -42,14 db > ; ? ? ? ? ? = ag_init 128 10 + g1806 , + 20 -------------------------- - g 6 02 db , < ; 10 g602 , ? 20 ----------------------- g 6 02 db , > ; ? ? ? ? ? =
psb 2170 detailed register description preliminary data sheet 189 10.99 5b h agc2 automatic gain control 2 speedl the parameter speedl for a multiplication factor m is given by the following formula: speedh the parameter speedh for a multiplication factor m is given by the following formula: 15 0 speedl speedh speedl m 8192 = speedh m 256 =
psb 2170 detailed register description preliminary data sheet 190 10.99 5c h agc3 automatic gain control 3 ag_gain the parameter ag_gain for a gain g ([db]) can be calculated by the following formula: ag_att the parameter ag_att for an attenuation a ([db]) can be calculated by the following formula: 15 0 ag_gain ag_att ag_gain 128 10 + g18.06 + 20 -------------------------- - g24db < ; 10 g6.02 ? 20 ---------------------- - g24db > ; ? ? ? ? ? = ag_att 10 a42.14 + 20 ------------------------- - =
psb 2170 detailed register description preliminary data sheet 191 10.99 5d h agc4 automatic gain control 4 dec the parameter dec for a time constant t ([1/ms]) is given by the following formula: lim the parameter lim for a signal level l ([db]) can be calculated by the following formula: 15 0 dec lim dec 256 t --------- - = lim 128 10 + l90.3 + 20 --------------------- - l50db ? < ; 10 l66.22 + 20 ------------------------- 25 ? l50db ? >> ; ? ? ? ? ? =
psb 2170 detailed register description preliminary data sheet 192 10.99 5e h agc5 automatic gain control 5 lp the parameter lp for a time constant t ([1/ms]) is given by the following formula: note: the value for lp should be at least 80 h (i.e., t<4ms) in order to avoid that the agc becomes instable. 15 0 00000000 lp lp 16 t ------ =
psb 2170 detailed register description preliminary data sheet 193 10.99 60 h r sctl speakerphone control ens enable echo suppression 0: the echo suppression unit is disabled 1: the echo suppression unit is enabled qu echo cancellation quality mode ewf enable wiener filter 0: the wiener filter is disabled 1: the wiener filter is enabled (in subband mode only) nad noise adaptation 0: noise adaptation is disabled. 1: noise adaptation is enabled. nr noise reduction enable 0: noise reduction disabled 1: noise reduction enabled 15 0 ens qu ewf nad nr cn md sdr sdx erd 0 agr agx 0 reset value 0 0 000000000000 14 13 12 description 0 0 0 echo cancellation disabled (half duplex) 0 0 1 subband, rnr 0 1 0 fullband mode one (similar to psb 2170 version 1.1) 0 1 1 fullband mode two 1 0 0 subband, reduced filter length 1 0 1 subband, analog line mode 1 1 0 subband, isdn mode 1 1 1 subband, enhanced mode detailed register description
psb 2170 detailed register description preliminary data sheet 194 10.99 cn comfort noise 0: the comfort noise generator is disabled. 1: the comfort noise generator is enabled. md mode 0: speakerphone mode 1: loudhearing mode sdr signal source of sdr 0: after agcr 1: before agcr sdx signal source of sdx 0: after agcx 1: before agcx erd enable reduced delay 0: normal operation in fullband mode two 1: the delay of fullband mode two is reduced agr agcr enable 0: agcr disabled 1: agcr enabled agx agcx enable 0: agcx disabled 1: agcx enabled
psb 2170 detailed register description preliminary data sheet 195 10.99 62 h r ssrc1 speakerphone source 1 i1 input signal selection (acoustic source 1) i2 input signal selection (acoustic source 2) 15 0 000000 i1 i2 reset value 000000 0 0
psb 2170 detailed register description preliminary data sheet 196 10.99 63 h r ssrc2 speakerphone source 2 i3 input signal selection (line source 1) i4 input signal selection (line source 2) 15 0 000000 i3 i4 reset value 000000 0 0
psb 2170 detailed register description preliminary data sheet 197 10.99 64 h ssdx1 speech detector (transmit) 1 lp2l the parameter lp2l for a saturation level l ([db]) can be calculated by the following formula: reset and default value for l : 20 db lim the parameter lim for a minimum signal level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -52 db 15 0 0lp2l0 lim reset value 1b3a h lp2l 2l 5 log2 -------------------- = lim 296.3l ? () 5log2 ---------------------------------- - =
psb 2170 detailed register description preliminary data sheet 198 10.99 65 h ssdx2 speech detector (transmit) 2 lp1 the parameter lp1 for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 4 ms off the parameter off for a level offset of o ([db]) can be calculated by the following formula: reset and default value for o : 4.5 db 15 0 lp1 0 off reset value 1006 h lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = off 2o 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 199 10.99 66 h ssdx3 speech detector (transmit) 3 pdn the parameter pdn for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32 ms lp2n the parameter lp2n for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32 ms 15 0 pdn lp2n reset value c0c0 h pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? =
psb 2170 detailed register description preliminary data sheet 200 10.99 67 h ssdx4 speech detector (transmit) 4 pds the parameter pds for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 102 ms lp2s the parameter lp2s for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 6.5 s 15 0 pds 0 lp2s reset value 9428 h pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2s 262144 t ------------------- - =
psb 2170 detailed register description preliminary data sheet 201 10.99 68 h ssdr1 speech detector (receive) 1 lp2l the parameter lp2l for a saturation level l ([db]) can be calculated by the following formula: reset and default value for l : 15 db lim the parameter lim for a minimum signal level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -55 db 15 0 0lp2l0 lim reset value 1437 h lp2l 2l 5 log2 -------------------- = lim 296.3l ? () 5log2 ---------------------------------- - =
psb 2170 detailed register description preliminary data sheet 202 10.99 69 h ssdr2 speech detector (receive) 2 lp1 the parameter lp1 for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 4 ms off the parameter off for a level offset of o ([db]) can be calculated by the following formula: reset and default value for o : 4.5 db 15 0 lp1 0 off reset value 1006 h lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = off 2o 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 203 10.99 6a h ssdr3 speech detector (receive) 3 pdn the parameter pdn for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32 ms lp2n the parameter lp2n for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32 ms 15 0 pdn lp2n reset value c0c0 h pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? =
psb 2170 detailed register description preliminary data sheet 204 10.99 6b h ssdr4 speech detector (receive) 4 pds the parameter pds for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 102 ms lp2s the parameter lp2s for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 6.5 s 15 0 pds 0 lp2s reset value 9428 h pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2s 262144 t ------------------- - =
psb 2170 detailed register description preliminary data sheet 205 10.99 6c h sscas1 speech comparator (acoustic side) 1 g the parameter g for a gain a ([db]) can be calculated by the following formula: reset and default value for a : 6 db note: the parameter g is interpreted in two?s complement. et the parameter et for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 0 ms 15 0 get reset value 0800 h g 2a 5log2 -------------------- = et t 4 -- - =
psb 2170 detailed register description preliminary data sheet 206 10.99 6d h sscas2 speech comparator (acoustic side) 2 gdn the parameter gdn for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 6 db pdn the parameter pdn for a decay rate r ([ms/db]) can be calculated by the following formula: reset and default value for r : 7 ms/db 15 0 0gdn pdn reset value 1006 h gdn 4g 5log2 -------------------- = pdn 64 5 log2 r ------------------------------- =
psb 2170 detailed register description preliminary data sheet 207 10.99 6e h sscas3 speech comparator (acoustic side) 3 gds the parameter gds for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 6 db pds the parameter pds for a decay rate r ([ms/db]) can be calculated by the following formula: reset and default value for r : 7 ms/db 15 0 0gds pds reset value 1006 h gds 4g 5 log2 -------------------- = pds 64 5log2r ------------------------------- =
psb 2170 detailed register description preliminary data sheet 208 10.99 6f h sscls1 speech comparator (line side) 1 g the parameter g for a gain a ([db]) can be calculated by the following formula: reset and default value for a : 0 db note: the parameter g is interpreted in two ? s complement. et the parameter et for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 0db 15 0 get reset value 0000 h g 2a 5log2 -------------------- = et t 4 -- - =
psb 2170 detailed register description preliminary data sheet 209 10.99 70 h sscls2 speech comparator (line side) 2 gdn the parameter gdn for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 12 db pdn the parameter pdn for a decay rate r ([ms/db]) can be calculated by the following formula: reset and default value for r : 21.3 ms/db 15 0 0gdn pdn reset value 2002 h gdn 4g 5log2 -------------------- = pdn 64 5 log2 r ------------------------------- =
psb 2170 detailed register description preliminary data sheet 210 10.99 71 h sscls3 speech comparator (line side) 3 gds the parameter gds for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 12 db pds the parameter pds for a decay rate r ([ms/db]) can be calculated by the following formula: reset and default value for r : 21.3 ms/db 15 0 0gds pds reset value 2002 h gds 4g 5 log2 -------------------- = pds 64 5log2r ------------------------------- =
psb 2170 detailed register description preliminary data sheet 211 10.99 72 h satt1 attenuation unit 1 att the parameter att for an attenuation a ([db]) can be calculated by the following formula: reset and default value for a : 36 db sw the parameter sw for a switching rate r ([ms/db]) can be calculated by the following formula: reset and default value for r : 0.1 ms/db 15 0 0att sw reset value 2c6a h att 2a 5 log2 -------------------- = sw 128 1 5log2 r ------------------------------- + 0.0053 r 0.66 << ; 16 5log2 r ------------------------------- 0.66 r 0.63 << ; ? ? ? ? ? =
psb 2170 detailed register description preliminary data sheet 212 10.99 73 h satt2 attenuation unit 2 tw the parameter tw for a time t ([ms]) can be calculated by the following formula: ds the parameter ds for a decay rate r ([ms/db]) can be calculated by the following formula: note: the value 0xff for the parameter ds specifies an infinite decay rate. therefore the speakerphone will not return to the idle state in the absence of speech signals. it will remain in the current state until a speech signal is detected and a state change is necessary. this is also the reset and default value. 15 0 tw ds reset value 0aff h tw t 16 ------ = ds 5log2 r1 ? 4 ---------------------------------------- =
psb 2170 detailed register description preliminary data sheet 213 10.99 74 h sagx1 automatic gain control (transmit) 1 ag_init the parameter ag_init for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 0 db note: this parameter is interpreted in two ? s complement. com the threshold com for a level l ([db]) can be calculated by the following formula: reset and default value for l : -24 db 15 0 ag_init 0 com reset value 005f h ag_init 2 ? g 5log2 -------------------- = com 296.3l + () 5 log2 ----------------------------------- =
psb 2170 detailed register description preliminary data sheet 214 10.99 75 h sagx2 automatic gain control (transmit) 2 ag_att the parameter ag_att for an attenuation a ([db]) can be calculated by the following formula: reset and default value for g : 96 db speedh the parameter speedh for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration ([db]). reset and default value for r : 2 ms/db 15 0 0 ag_att speedh reset value 7fff h ag_att 2a ? 5log2 -------------------- = speedh 512 dr -------------- =
psb 2170 detailed register description preliminary data sheet 215 10.99 76 h sagx3 automatic gain control (transmit) 3 ag_gain the parameter ag_gain for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 0 db speedl the parameter speedl for the regulation speed r ([ms/db]) can be calculated by the following formula: the variable d denotes the aberration ([db]). reset and default value for r : 160 ms/db 15 0 ag_gain speedl reset value 0014 h ag_gain 2 ? g 5log2 -------------------- = speedl 4096 dr -------------- =
psb 2170 detailed register description preliminary data sheet 216 10.99 77 h sagx4 automatic gain control (transmit) 4 nois the parameter nois for a threshold level l ([db]) can be calculated by the following formula: reset and default value for l : -48 db lpa the parameter lpa for a low pass time constant t ([ms]) can be calculated by the following formula: reset and default value for t : 2 ms 15 0 0nois0 lpa reset value 4020 h nois 2 96.3 l + () 5log2 ----------------------------------- = lpa 16 t ------ =
psb 2170 detailed register description preliminary data sheet 217 10.99 78 h sagx5 automatic gain control (transmit) 5 ag_cur the current gain g of the agcx can be derived from the parameter parameter ag_cur by the following formula: note: ag_cur is interpreted in two ? s complement. 15 0 ag_cur 00000000 g 5 ? log2 ag_cur 2 ------------------------------------------------------ - =
psb 2170 detailed register description preliminary data sheet 218 10.99 79 h sagr1 automatic gain control (receive) 1 ag_init the parameter ag_init for a gain g ([db]) can be calculated by the following formula: this parameter is interpreted in two ? s complement. reset and default value for g : 0 db com the parameter com for a threshold l ([db]) can be calculated by the following formula: this parameter is interpreted in two ? s complement. reset and default value for l : -12 db 15 0 ag_init com reset value 006f h ag_init 2 ? g 5log2 -------------------- = com 296.3l + () 5 log2 ----------------------------------- =
psb 2170 detailed register description preliminary data sheet 219 10.99 7a h sagr2 automatic gain control (receive) 2 ag_att the parameter ag_att for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 96 db speedh the parameter speedh for the regulation speed r ([ms/db]) can be calculated by the following formula: the variable d denotes the aberration ([db]). reset and default value for r : 2 ms/db 15 0 0 ag_att speedh reset value 7fff h ag_att 2 ? g 5log2 -------------------- = speedh 512 dr -------------- =
psb 2170 detailed register description preliminary data sheet 220 10.99 7b h sagr3 automatic gain control (receive) 3 ag_gain the parameter ag_gain for a gain g ([db]) can be calculated by the following formula: reset and default value for g : 0 db speedl the parameter speedl for the regulation speed r ([ms/db]) can be calculated by the following formula: the variable d denotes the aberration ([db]). reset and default value for r : 200 ms/db 15 0 ag_gain speedl reset value 001a h ag_gain 2 ? g 5log2 -------------------- = speedl 4096 dr -------------- =
psb 2170 detailed register description preliminary data sheet 221 10.99 7c h sagr4 automatic gain control (receive) 4 nois the parameter nois for a threshold level l ([db]) can be calculated by the following formula: reset and default value for l : -48 db lpa the parameter lpa for a low pass time constant t ([ms]) can be calculated by the following formula: reset and default value for t : 2 ms 15 0 0nois0 lpa reset value 4020 h nois 296.3l + () 5log2 ----------------------------------- = lpa 16 t ------ =
psb 2170 detailed register description preliminary data sheet 222 10.99 7d h sagr5 automatic gain control (receive) 5 ag_cur the current gain g of the agcr can be derived from the parameter parameter ag_cur by the following formula: ag_cur is interpreted in two ? s complement. 15 0 ag_cur 00000000 g 5 ? log2 ag_cur 2 ------------------------------------------------------ - =
psb 2170 detailed register description preliminary data sheet 223 10.99 7e h slga line gain lgar the parameter lgar for a gain g ([db]) is given by the following formula: reset and default value for g : 6 db lgax the parameter lgax for a gain g ([db]) is given by the following formula: reset and default value for g : 6 db 15 0 0lgar0lgax reset value 4040 h lgar 128 g12 ? () 20 ? 10 = lgax 128 g12 ? () 20 ? 10 =
psb 2170 detailed register description preliminary data sheet 224 10.99 7f h saelen acoustic echo cancellation length fblen len denotes the number of fir-taps used in fullband mode. 15 0 000000 fblen reset value 0200 h
psb 2170 detailed register description preliminary data sheet 225 10.99 80 h saeaw acoustic echo cancellation adaptation window fbada fbada denotes the number of fir-taps changed adaptively in full band mode. 15 0 0000000 fbada reset value 0100 h
psb 2170 detailed register description preliminary data sheet 226 10.99 81 h saeel acoustic echo cancellation reported attenuation limit aeclim the maximum value for an attenuation a ([db]) of the echo cancellation unit reported to the echo suppression unit given by the following formula: reset and default value is the maximum value for a . 15 0 0 aeclim reset value 7ffff h aeclim 512 a 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 227 10.99 82 h saedtr acoustic echo cancellation double talk reduction aecatt the parameter aecatt for an attenuation reduction a ([db]) during double talk is given by the following formula: reset and default value for a : 15 db 15 0 0 aecatt reset value 1400 h aecatt 512 a 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 228 10.99 83 h saedtl acoustic echo cancellation double talk limit aecdtm the parameter aecdtm for a minimum energy a ([db]) during double talk is given by the following formula: reset and default value for a : 16 db 15 0 0 aecdtm reset value 1800 h aecdtm 512 a 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 229 10.99 84 h saedti acoustic echo cancellation double talk increment aecdti aecdti determines the rate the attenuation reduction red ([db/s]) of the aec is incremented with when double talk is detected: reset and default value for a : 31.6 db/s 15 0 0 aecdti reset value 0100 h aecdti red 8.192 -------------- - =
psb 2170 detailed register description preliminary data sheet 230 10.99 85 h saedtd acoustic echo cancellation double talk decrement aecdtd aecdtd determines the rate the attenuation reduction red of the aec is decremented with when double talk is detected: reset and default value for red : 12 db/s 15 0 0 aecdtd reset value 0062 h aecdtd red 8.192 -------------- - =
psb 2170 detailed register description preliminary data sheet 231 10.99 86 h saewfl wiener filter limit attenuation afatt the parameter wfatt for a maximal attenuation a ([db]) of the wiener filter is given by the following formula: reset and default value for a : 60 db 15 0 0wfatt reset value 5000 h limit 512 a 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 232 10.99 87 h snratt noise reduction attenuation nratt noise reduction attenuation the maximum attenuation a of frequencies with a high noise to signal ratio performed by the noise reduction unit can be calculated by the following formula: reset and default value for a : 15 db 15 0 0 nratt reset value 2800 h nratt 32768 a db 20 ------- ? 10 =
psb 2170 detailed register description preliminary data sheet 233 10.99 88 h snrlnl noise reduction lower noise limit nrlow noise reduction lower limit the level l ([db]) of the noise to deactive the coupling between the wiener filter and the noise reduction unit can be calculated by the following formula: reset and default value for l : -48 db 15 0 0 nrlow reset value 4000 h nrlow 512 96.3 l + () 5log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 234 10.99 89 h snrunl noise reduction upper noise limit nrup noise reduction upper limit the level l ([db]) of the noise to active the coupling between the wiener filter and the noise reduction unit can be calculated by the following formula: reset and default value for l : -36 db 15 0 0 nrup reset value 5000 h nrup 512 96.3 l + () 5 log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 235 10.99 90 h scsd1 speech detector (comfort noise) 1 lp2l the parameter lp2l for a saturation level l ([db]) can be calculated by the following formula: reset and default value for l : 25 db lim the parameter lim for a minimum signal level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -65 db 15 0 0lp2l0 lim reset value 7f29 h lp2l 2l 5 log2 -------------------- = lim 296.3l + () 5log2 ----------------------------------- =
psb 2170 detailed register description preliminary data sheet 236 10.99 91 h scsd2 speech detector (comfort noise) 2 lp1 the parameter lp1 for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 4 ms off the parameter off for a level offset of o ([db]) can be calculated by the following formula: reset and default value for o : 4.5 db 15 0 lp1 0 off reset value 1006 h lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = off 2o 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 237 10.99 92 h scsd3 speech detector (comfort noise) 3 pdn the parameter pdn for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32 ms lp2n the parameter lp2n for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 32ms 15 0 pdn lp2n reset value 0202 h pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? =
psb 2170 detailed register description preliminary data sheet 238 10.99 93 h scsd4 speech detector (comfort noise) 4 pds the parameter pds for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 203 ms lp2s the parameter lp2s for a time t ([ms]) can be calculated by the following formula: reset and default value for t : 3 s 15 0 pds 0 lp2s reset value 9457 h pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; ? ? ? = lp2s 262144 t ------------------- - =
psb 2170 detailed register description preliminary data sheet 239 10.99 94 h sclpt low pass time constant tc the parameter tc for a time constant t ([ms]) can be calculated by the following formula: reset and default value for t : 2 s note: tc must be greater than zero. 15 0 0tc reset value 0020 h tc 65534 t ---------------- =
psb 2170 detailed register description preliminary data sheet 240 10.99 95 h sccr correlation corr the parameter corr for a linear correlation c is given by: reset and default value for c : 0.97 note: corr must be greater than 0x4fff. this means that a 1 has to be programmed to bit 14. 15 0 0 1 corr reset value 7c28 h corr 32768 c =
psb 2170 detailed register description preliminary data sheet 241 10.99 96 h sccrn correlation noise threshold nth the parameter nth for a threshold l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -60 db 15 0 0nth reset value 3000 h nth 512 96.3 l + () 5 log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 242 10.99 97 h sccrs correlation sensitivity cs the parameter cs for a sensitivity se ([1/db]) can be calculated by the following formula: reset and default value for se : -0.00425 1/db note: the parameter cs is interpreted in two ? s complement. note: the bits 12 to 15 have to be set to 1. 15 0 1111 cs reset value fccd h cs 655350 2 () log se =
psb 2170 detailed register description preliminary data sheet 243 10.99 98 h sccrl correlation limit limit the parameter limit for a correlation limit l is given by: reset and default value for l : 0.850 db note: l must be greater than 0x4fff. thus, bit 14 must be set to 1. 15 0 01 limit reset value 6ccc h limit 32768 l =
psb 2170 detailed register description preliminary data sheet 244 10.99 99 h scdtn double talk detection threshold nth the parameter nth for a noise threshold l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -60 db 15 0 0nth reset value 2200 h nth 512 96.3 l + () 5 log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 245 10.99 9a h scdts double talk sensitivity dts the parameter dts for a sensitivity se ([1/db]) can be calculated by the following formula: reset and default value for se : -0.3 db/db note: the parameter se is interpreted in two ? s complement. note: the bits 12 to 15 have to be set to 1. 15 0 1111 dts reset value fd9a h s 2048 se =
psb 2170 detailed register description preliminary data sheet 246 10.99 9b h scdtl double talk limit limit the parameter limit for a level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : 12 db note: limit must be greater than 0x7ff. 15 0 0 limit reset value 1000 h limit 512 l 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 247 10.99 9c h scattn attenuation noise nth the parameter nth for a threshold l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : -60 db 15 0 0nth reset value 3000 h nth 512 96.3 l + () 5 log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 248 10.99 9d h scatts attenuation sensitivity as the parameter as for a sensitivity se ([1/db]) can be calculated by the following formula: reset and default value for se : 1 db/db 15 0 0as reset value 0800 h as 2048 se =
psb 2170 detailed register description preliminary data sheet 249 10.99 9e h scattl attenuation limit limit the parameter limit for a level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and default value for l : 42 db note: limit must be greater than 0x7ff. 15 0 0limit reset value 3800 h limit 512 l 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 250 10.99 9f h sclspn loudspeaker noise nth the parameter nth for a threshold l ([db], relative to pcm max. value) can be calculated by the following formula: reset and cautious value for l : -44 db 15 0 0nth reset value 442a h nth 512 96.3 l + () 5 log2 ------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 251 10.99 a0 h sclsps loudspeaker sensitivity gs the parameter gs for a sensitivity se ([1/db]) can be calculated by the following formula: reset and cautious value for se : 0.25 db/db 15 0 0gs reset value 0200 h gs 2048 se =
psb 2170 detailed register description preliminary data sheet 252 10.99 a1 h sclspl loudspeaker limit limit the parameter limit for a level l ([db], relative to pcm max. value) can be calculated by the following formula: reset and cautious value for l : 6 db note: limit must be greater than 0x7ff. 15 0 0 limit reset value 0800 h limit 512 l 5log2 -------------------- =
psb 2170 detailed register description preliminary data sheet 253 10.99 a2 h sccn1 comfort noise constant level const the parameter const controls the level of the comfort noise. the range is from 0 (off) to 32767 (max.). the parameter has linear behavior. 15 0 0const reset value 0000 h
psb 2170 detailed register description preliminary data sheet 254 10.99 a3 h sccn2 comfort noise multiplication factor fac the parameter fac for a factor f can be calculated by the following formula: 15 0 0fac reset value 0600 h fac 2048 f =
psb 2170 detailed register description preliminary data sheet 255 10.99 a4 h sccn3 comfort noise low pass lp the parameter lp for a time constant ts ([1/ms]) can be calculated by the following formula: 15 0 0lp reset value 0800 h lp 983.025 ts --------------------- =
psb 2170 detailed register description preliminary data sheet 256 10.99 a6 h r nrctl noise reduction control en noise reduction enable 0: disabled 1: enabled md speakerphone mode dependence i1 input signal selection 15 0 en md 00000000 i1 reset value 0 0 00000000 0 14 13 speakerphone mode description 0 0 fullband mode one number of taps must be restricted to 447 fullband mode two not allowed subband mode not allowed 0 1 fullband mode one not allowed fullband mode two number of taps must be reduced to 414 subband mode mode "rnr" must be selected 1 0 fullband mode one there must be disabled (isdn mode): dtmf, at, cpt, ut detectors, cid, na, cn and lec fullband mode two number of taps up to 645, but there must be disabled (isdn mode): dtmf, at, cpt, ut detectors, cid, na, cn and lec subband mode subband modes "normal", "reduced" or "rnr" are allowed, but there must be disabled (isdn mode): dtmf, at, cpt, ut detectors, cid, na, cn and lec 11 reserved
psb 2170 detailed register description preliminary data sheet 257 10.99 a7 h nratt noise reduction attenuation nratt noise reduction attenuation the maximum attenuation a ([db]) of noisy frequencies performed by the noise reduction unit can be calculated by the following formula: 15 0 0 nratt nratt 32768 a 20 ------ ? 10 =
psb 2170 detailed register description preliminary data sheet 258 10.99 a8 h r utdctl universal tone detector control en utd detector enable 0: disabled 1: enabled i1 input signal selection 15 0 en0000000000 i1 reset value 00000000000 0
psb 2170 detailed register description preliminary data sheet 259 10.99 a9 h utdcf center frequency for utd cf the parameter cf for a center frequency f (hz) can be calculated by the following formula: 15 0 cf cf 32768 2 f 8000 -------------------- ?? ?? cos =
psb 2170 detailed register description preliminary data sheet 260 10.99 aa h utdbw band width for utd bw the parameter bw for a band width b (hz) can be calculated by the following formula: 15 0 0bw bw 65536 b 8000 ? () tan 1 b 8000 ? () tan + ------------------------------------------------------ =
psb 2170 detailed register description preliminary data sheet 261 10.99 ab h utdlim limiter limit for utd lim signal limit the parameter lim for a limit of l[db] can be calculated by the following formula: 15 0 0lim lim 32768 l20 ? 10 =
psb 2170 detailed register description preliminary data sheet 262 10.99 ac h utdlev minimal signal level for utd lev minimal level of signal the parameter lev for a minimum in-band signal level of l[db] can be calculated by the following formula: 15 0 0lev lev 32768 l20 ? 10 =
psb 2170 detailed register description preliminary data sheet 263 10.99 ad h utddlt minimum difference for utd delta minimal difference between in-band signal and out-of-band signal the parameter delta for a signal difference of d [db] can be calculated by the following formula: 15 0 delta delta d () sgn 32768 d () 20 ? ? 10 =
psb 2170 detailed register description preliminary data sheet 264 10.99 ae h utdtmt tone times for utd ttone minimum time for activation the parameter ttone for a minimal activation time t [ms] can be calculated by the following formula: tb1 maximum break time for ttone the parameter tb1 for a maximum break time is given in milliseconds. 15 0 ttone tb1 ttone t 8 -- - =
psb 2170 detailed register description preliminary data sheet 265 10.99 af h utdtmg gap times for utd tgap minimum time for deactivation the parameter tgap for a minimal deactivation time t [ms] can be calculated by the following formula: tb2 maximum break time for tgap the parameter tb2 for a maximum break time is given in milliseconds. 15 0 tgap tb2 tgap t 8 -- - =
psb 2170 detailed register description preliminary data sheet 266 10.99
psb 2170 detailed register description preliminary data sheet 267 10.99 b0 h r cidmf1 caller id message format mf message format valid start byte. 15 0 0mf reset value 00 detailed register description
psb 2170 detailed register description preliminary data sheet 268 10.99 b1 h r cidmf2 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 2170 detailed register description preliminary data sheet 269 10.99 b2 h r cidmf3 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 2170 detailed register description preliminary data sheet 270 10.99 b3 h r cidmf4 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 2170 detailed register description preliminary data sheet 271 10.99 b4 h r cidmf5 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 2170 detailed register description preliminary data sheet 272 10.99 b5 h r cidmf6 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 2170 electrical characteristics preliminary data sheet 273 10.99 6 electrical characteristics electrical characteristics 6.1 absolute maximum ratings esd integrity (according mil-std. 883d, method 3015.7): 2 kv note: conditions: maximum ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the "recommended operating conditions" is not guaranteed. stresses above the maximum ratings are likely to cause permant damage. 6.2 dc characteristics parameter symbol limit values unit ambient temperature under bias t a -20 to 85 c storage temperature t stg ? 65 to125 c supply voltage v dd -0.5 to 4.2 v supply voltage v dda -0.5 to 4.2 v voltage of pin with respect to ground: xtal 1 , xtal 2 v s -0.3 to 3.6 v voltage on any pin with respect to ground (except xtal 1 , xtal 2 ) v s - 0.5 to 5.5 1) 1) the difference from the minumum to the maximum value for v s /v dd /v ss at any pin must never exceed 5.5 v. v v dd / v dda = 3.3 v 0.3 v; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. input leakage current i il ? 1.0 1.0 a0v v in v dd h-input level (except xtal 1 ) v ih1 2.0 5.5 v h-input level (xtal 1 ) v ih2 0.8 v dd v dda + 0.3 v l-input level (except xtal 1 ) v il1 ? 0.3 0.8 v l-input level (xtal 1 ) v il2 ? 0.3 0.2 v dda v h-output level (except du/dx, dd/ dr, gp 0 -gp 15 , sps 0 , sps 1 , int ) v oh1 v dd ? 0.45 v i o = 2 ma h-output level (sps 0 , sps 1 , sdx, gp 0 -gp 15 , int ) v oh2 v dd ? 0.6 v i o = 2ma h-output level (du/dx, dd/dr) v oh4 v dd ? 0.6 v i o = 7 ma
psb 2170 electrical characteristics preliminary data sheet 274 10.99 6.3 ac characteristics digital inputs are driven to 2.4 v for a logical ? 1 ? and to 0.45 v for a logical ? 0 ? . timing measurements are made at 2.0 v for a logical ? 1 ? and 0.8 v for a logical ? 0 ? . the ac- testing input/output waveforms are shown below. figure 67 input/output waveforms for ac-tests l-output level (except du/dx, dd/ dr, ma 0 -ma 15 ) v ol1 0.45 v i o = ? 2 ma l-output level (gp 0 -gp 15 ) v ol2 0.45 v i o = ? 5 ma l-output current (gp 0 -gp 15 ) (after reset) i lo 55 102 160 arst=1 l-output level (du/dx, dd/dr) v ol3 0.45 v i o = ? 7 ma input capacitance c i 10 pf output capacitance c o 15 pf v dd +v dda supply current (powerdown) i dds1 10 50 a v dd +v dda supply current (operating) i ddo 40 70 ma v dd = 3.3 v v dd / v dda = 3.3 v 0.3 v; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max.
psb 2170 electrical characteristics preliminary data sheet 275 10.99 timing dtmf detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -1.5 1.5 % frequency deviation reject 3.5 -3.5 % acceptance level -45 0 db rel. to max. pcm rejection level -50 db rel. to max. pcm twist deviation accept +/-2 +/-8 db programmable noise tolerance 12 db signal duration accept 40 ms signal duration reject 19 ms gap duration accept 23 ms caller id decoder parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -2 2 % acceptance level -45 0 db rel. to max. pcm transmission rate 1188 1200 1212 baud noise tolerance 12 db echo cancellation unit (subband mode) subband (hz) filter length (ms) lower limit upper limit rnr reduced analog isdn enhanced 0 250 45 60 97 118 126 250 750 50 66 111 159 159 750 1250 50 64 87 109 123 1250 1750 45 60 60 76 88 1750 2250 40 54 60 76 88 2250 2750 36 48 57 72 82 2750 3250 34 42 30 43 54 3250 3750 33 42 30 43 54
psb 2170 electrical characteristics preliminary data sheet 276 10.99 alert tone detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -0.5 0.5 % atdctl1:dev=0 frequency deviation accept -1.1 1.1 % atdctl1:dev=1 frequency deviation reject 3.5 -3.5 % acceptance level -40 0 db rel. to max. pcm rejection level -5 db rel. to acceptance level twist deviation accept +/-7 db noise tolerance 20 db signal duration accept 75 ms gap duration accept 40 ms atdctl1:gt=0 gap duration accept 12 ms atdctl1:gt=1
psb 2170 electrical characteristics preliminary data sheet 277 10.99 status register update time the individual bits of the status register may change due to an event (like a recognized dtmf tone) or a command. the timing can be divided into four classes with these definitions the timing of the individual bits in the status register can be given as shown in the following table: timing diagrams table 64 status register update timing class timing comment min. max. i 0 0 immediately after command has been issued a0 150 s command has been accepted d 125 s250 s deactivation time after command has been issued e - - associated event has happened bit rdy abt cia cd cpt cng dtv atv atc 0->1 aeeeeeeea 1->0 i a a,d e,d e,d d e,d e,d e,d
psb 2170 electrical characteristics preliminary data sheet 278 10.99 figure 68 oscillator circuit note: this generally recommended circuity and the values must be verified for each board design. please use the appropriate application note for doing so. furthermore, the provider of the crystal must be consulted for verification of the circuitry. recommended / maximum values oscillator circuit value unit min typ max crystal load capacity c l 12 pf ext. capacitors c 1 = c 2 @ 34.560mhz 5 8.2 12 pf ext. capacitors c 1 = c 2 @ 31.104mhz 5 1015pf static (parallel) capacitance x 1 7pf resonance resistance x 1 40 ? frequency deviation 500 1) 1) the frequency deviation must not exceed 500 ppm if afe clock tracking (bit act in register hwconfig1) is enabled. ppm xtal 1 xtal 2 c 1 c 2 x 1
psb 2170 electrical characteristics preliminary data sheet 279 10.99 figure 69 ssdi/iom ? -2 interface - bit synchronization timing figure 70 ssdi/iom ? -2 interface - frame synchronization timing parameter ssdi/iom ? -2 interface symbol limit values unit min max dcl period t 1 90 ns dcl high t 2 35 ns dcl low t 3 35 ns input data setup t 4 20 ns input data hold t 5 10 ns dd/dr dcl du/dx du/dx first bit last bit bit n bit n+1 t 4 t 6 t 7 t 8 t 5 t 2 t 1 t 3 fsc dcl t 9 t 10 t 9 t 10
psb 2170 electrical characteristics preliminary data sheet 280 10.99 output data from high impedance to active (fsc high or other than first timeslot) t 6 30 ns output data from active to high impedance t 7 30 ns output data delay from clock t 8 30 ns fsc setup t 9 40 ns fsc hold t 10 40 ns fsc jitter (deviation per frame) -200 200 ns parameter ssdi/iom ? -2 interface symbol limit values unit min max
psb 2170 electrical characteristics preliminary data sheet 281 10.99 figure 71 ssdi interface - strobe timing parameter ssdi interface symbol limit values unit min max dxst delay t 1 20 ns drst inactive setup t 2 20 ns drst inactive hold t 3 20 ns drst active setup t 4 20 ns drst active hold t 5 20 ns fsc setup t 6 8 dcl cycles fsc hold t 7 40 ns drst dcl t 4 t 5 t 2 t 3 fsc t 6 t 7 dxst t 1
psb 2170 electrical characteristics preliminary data sheet 282 10.99 figure 72 sci interface parameter sci interface symbol limit values unit min max sclk cycle time t 1 500 ns sclk high time t 2 100 ns sclk low time t 3 100 ns cs setup time t 4 40 ns cs hold time t 5 10 ns sdr setup time t 6 40 ns sdr hold time t 7 40 ns sdx data out delay t 8 80 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 80 ns sclk to sdx tristate t 11 40 ns cs to int delay t 12 80 ns cs sclk sdr sdx int t 4 t 2 t 3 t 1 t 12 t 10 t 11 t 9 t 5 t 6 t 7 t 8
psb 2170 electrical characteristics preliminary data sheet 283 10.99 figure 73 analog front end interface parameter afe interface symbol limit values unit min max afeclk period (hwconfig3:cm0=0) t 1 13.5*p 1) /f xtal -10 1) the factor p is determined by hwconfig1:xtal (see register description) 13.5*p/f xtal +10 ns afeclk period (hwconfig3:cm0=1) t 1 4.5*p/f xtal -10 4.5*p/f xtal +10 ns afeclk high t 2 41/f xtal afeclk low t 3 41/f xtal afedu setup t 4 20 ns afedu hold t 5 20 ns afedd output delay t 6 30 ns afefs output delay t 7 30 ns afedu afeclk afedd bit n bit n+1 t 4 t 6 t 5 t 2 t 1 t 3 afefs t 7 t 7
psb 2170 electrical characteristics preliminary data sheet 284 10.99 figure 74 general purpose parallel port - multiplex mode parameter general purpose parallel port - multiplex mode symbol limit values unit min typ max active time (gp 0 -gp 15 ) t 1 2ms gap time (gp 0 -gp 15 ) t 2 125 s data setup time t 3 50 ns data hold time t 4 0ns gp 0 -gp 11 gp 12 t 3 t 4 t 1 t 2 gp 13
psb 2170 electrical characteristics preliminary data sheet 285 10.99 figure 75 reset timing parameter reset timing symbol limit values unit min max v dd / v dda rise time 5%-95% t 1 20 ms supply voltages stable to rst high t 2 0ns supply voltages stable to rst low t 3 0.1 ms rst high time t 4 1000 ns rst t 3 v dd / v ddp t 1 t 2 t 4
psb 2170 package outlines preliminary data sheet 286 10.99 7 package outlines plastic package, p-mqfp-80 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our dimensions in mm smd = surface mounted device
psb 2170 semiconductor group 287 a abort clearing event 79, 111 functional description 79 status bit 101 alert tone detector electrical characteristics 275 functional description 60 registers 134 ? 135 analog front end interface electrical characteristics 283 functional description 66 registers 114 ? 120 timing 91 automatic gain control functional description 69 registers 186 ? 192 auxiliary parallel port multiplex mode 98 c caller id decoder electrical characteristics 275 functional description 63 registers 136 ? 137 comfort noise adaptation 49 generation 47 cpt detector functional description 58 registers 140 ? 144, 174, 175, 256 status bit 101 d digital interface functional description 67 mode bit 104 modes 85 pin mode 102 registers 121 ? 127, 139 dtmf detector electrical characteristics 275 functional description 57 registers 149 ? 151 dtmf generator functional description 65 registers 129 ? 133 e equalizer functional description 71 registers 152 ? 157 g general purpose parallel port electrical characteristics 284 mode bits 104 registers 177 ? 182 static mode 98 group listening 44 h hardware configuration functional description 79 registers 102 i interrupt functional description 78 pin mode 102 register 113 iom ? -2 interface electrical characteristics 279 ? 280 functional description 85 see also: digital interface l line echo canceller functional description 55 registers 145 ? 148 o oscillator electrical characteristics 278 mode bits 104 p power down functional description 77 status bit 103 r reset
psb 2170 semiconductor group 288 electrical characteristics 285 functional description 77 restrictions modules 80 revision functional description 79 register 111 s serial control interface command opcodes 96 electrical characteristics 282 functional description 93 pin mode 102 speakerphone automatic gain control 44 echo suppression 32, 34 electrical characteristics 275 fullband mode 27, 28 loudhearing 44 overview 26 registers 193 ? 255 speech comparator 40 speech detector 37 subband mode 31 sps outputs functional description 44, 77 register 176 ssdi interface electrical characteristics 279 ? 281 functional description 89 see also: digital interface status register definition 101 update timing 277 t tone generator functional description 73 registers 158 ? 173 u universal attenuator functional description 69 register 128

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